A 30mW 12b 40MS/s subranging ADC with a high-gain offset-canceling positive-feedback amplifier in 90nm digital CMOS. - Yasuhide Shimizu; Shigemitsu Murayama; Kohhei Kudoh; Hiroaki Yatsuda; Akihide Ogawa (ISSCC, 2006)

A Split-Load Interpolation-Amplifier-Array 300MS/s 8b Subranging ADC in 90nm CMOS. - Yasuhide Shimizu; Shigemitsu Murayama; Kohhei Kudoh; Hiroaki Yatsuda (ISSCC, 2008)

Service Designs for Lifestyle Changes. - Yasuhide Shimizu; Kazuma Obata; Leo Wakiya; Daichi Aoki; Kazuhiro Kimura; Eichi Shibata; Toshiya Sasaki; Kazuhiko Yamazaki; Tomonori Yazaki; Kengo Fujita (HCI (28), 2013)