A 200-MFLOPS 100-MHz 64-b BiCMOS vector-pipelined processor (VPP) ULSI. - Fuyuki Okamoto; Yasuhiko Hagihara; Chie Ohkubo; Naoki Nishi; Hachiro Yamada; Tadayoshi Enomoto (IEEE J. Solid State Circuits, 1991)

Floating-point datapaths with online built-in self speed test. - Yasuhiko Hagihara; Shigeto Inui; Fuyuki Okamoto; Masato Nishida; Toshihiko Nakamura; Hachiro Yamada (IEEE J. Solid State Circuits, 1997)

Timing optimization by replacing flip-flops to latches. - Ko Yoshikawa; Yasuhiko Hagihara; Keisuke Kanamaru; Yuichi Nakamura 002; Shigeto Inui; Takeshi Yoshimura (ASP-DAC, 2004)

Redefinition of Write Margin for Next-Generation SRAM and Write-Margin Monitoring Circuit. - Koichi Takeda 001; Hidetoshi Ikeda; Yasuhiko Hagihara; Masahiro Nomura; Hiroyuki Kobatake (ISSCC, 2006)

An Automatic Bi-Directional Bus Repeater Control Scheme Using Dynamic Collaborative Driving Techniques. - Masahiro Nomura; Taku Ohsawa; Koichi Takeda 001; Yoetsu Nakazawa; Yoshinori Hirota; Yasuhiko Hagihara; Naoki Nishi (IEICE Trans. Electron., 2006)

Domino Logic Synthesis System and its Applications. - Ko Yoshikawa; Shigeto Inui; Yasuhiko Hagihara; Yuichi Nakamura 002; Takeshi Yoshimura (J. Circuits Syst. Comput., 2006)

Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes. - Masahiro Nomura; Yoshifumi Ikenaga; Koichi Takeda 001; Yoetsu Nakazawa; Yoshiharu Aimoto; Yasuhiko Hagihara (IEEE J. Solid State Circuits, 2006)

A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications. - Koichi Takeda 001; Yasuhiko Hagihara; Yoshiharu Aimoto; Masahiro Nomura; Yoetsu Nakazawa; Toshio Ishii; Hiroyuki Kobatake (IEEE J. Solid State Circuits, 2006)

A Circuit for Determining the Optimal Supply Voltage to Minimize Energy Consumption in LSI Circuit Operations. - Yoshifumi Ikenaga; Masahiro Nomura; Yoetsu Nakazawa; Yasuhiko Hagihara (IEEE J. Solid State Circuits, 2008)

Optical I/O core transmitter with high tolerance to optical feedback using quantum dot laser. - Kenji Mizutani; Kenichiro Yashiki; Mitsuru Kurihara; Yasuyuki Suzuki; Yasuhiko Hagihara; Nobuaki Hatori; Takanori Shimizu; Yutaka Urino; Takahiro Nakamura; Kazuhiko Kurata; Yasuhiko Arakawa (ECOC, 2015)

5 mW/Gbps hybrid-integrated Si-photonics-based optical I/O cores and their 25-Gbps/ch error-free operation with over 300-m MMF. - Kenichiro Yashiki; Yasuyuki Suzuki; Yasuhiko Hagihara; Mitsuru Kurihara; Masatoshi Tokushima; Junichi Fujikata; Akio Ukita; Koichi Takemura; Takanori Shimizu; Daisuke Okamoto; Jun Ushida; Shigeki Takahashi; et al. (OFC, 2015)

25-Gbps error-free operation of chip-scale Si-photonics optical transmitter over 70°C with integrated quantum dot laser. - Kenichiro Yashiki; Kenji Mizutani; Jun Ushida; Yasuyuki Suzuki; Mitsuru Kurihara; Masatoshi Tokushima; Junichi Fujikata; Yasuhiko Hagihara; Kazuhiko Kurata (OFC, 2016)

25-Gbps/ch Error-Free Operation over 300-m MMF of Low-Power-Consumption Silicon-Photonics-Based Chip-Scale Optical I/O Cores. - Kenichiro Yashiki; Toshinori Uemura; Mitsuru Kurihara; Yasuyuki Suzuki; Masatoshi Tokushima; Yasuhiko Hagihara; Kazuhiko Kurata (IEICE Trans. Electron., 2016)

Fingertip-Size Optical Module, "Optical I/O Core", and Its Application in FPGA. - Takahiro Nakamura; Kenichiro Yashiki; Kenji Mizutani; Takaaki Nedachi; Junichi Fujikata; Masatoshi Tokushima; Jun Ushida; Masataka Noguchi; Daisuke Okamoto; Yasuyuki Suzuki; Takanori Shimizu; Koichi Takemura; et al. (IEICE Trans. Electron., 2019)