Fuzzy inference and fuzzy inference processor. - Kazuo Nakamura; Narumi Sakashita; Yasuhiko Nitta; Ken'ichi Shimomura; Takeshi Tokuda (IEEE Micro, 1993)

A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture. - Narumi Sakashita; Yasuhiko Nitta; Ken'ichi Shimomura; Fumihiro Okuda; Hiroki Shimano; Satoshi Yamakawa; Masaki Tsukude; Kazutami Arimoto; Shinji Baba; Shinji Komori; Kazuo Kyuma; Akihiko Yasuoka; et al. (IEEE J. Solid State Circuits, 1996)