Top-down pass-transistor logic design. - Kazuo Yano; Yasuhiko Sasaki; Kunihito Rikino; Koichi Seki (IEEE J. Solid State Circuits, 1996)

ALPS: An Automatic Layouter for Pass-Transistor Cell Synthesis. - Yasuhiko Sasaki; Kunihito Rikino; Kazuo Yano (ASP-DAC, 1998)

Hole filling: a novel delay reduction technique using selector logic. - Shunzo Yamashita; Naoki Katoh; Yasuhiko Sasaki; Yohei Akita; Hidetoshi Chikata; Kazuo Yano (CICC, 1998)

Multi-aggressor relative window method for timing analysis including crosstalk delay degradation. - Yasuhiko Sasaki; Kazuo Yano (CICC, 2000)

Crosstalk delay analysis of a 0.13-μm node test chip and precise gate-level simulation technology. - Yasuhiko Sasaki; Mitsumasa Sato; Masaru Kuramoto; Fujio Kikuchi; Tsutomu Kawashima; Hiroo Masuda; Kazuo Yano (IEEE J. Solid State Circuits, 2003)

Constant-ratio-coupled multi-grain digital synchronizer with flexible input-output delay selection for versatility in low-power applications. - Yasuhiko Sasaki; Naoki Kato; Hiroaki Nakaya (IEEE J. Solid State Circuits, 2006)