Estimating the Propagation Velocity Distribution and the Position of Buried Pipe Using x -t - v Data Matrix of Subsurface Radar Image. - Yasuhiro Fujimura; Akira Kawanaka; Hideki Hayakawa (MVA, 1996)

A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry. - Keiichi Higeta; Masami Usami; Masayuki Ohayashi; Yasuhiro Fujimura; Masahiko Nishiyama; Satoru Isomura; Kunihiko Yamaguchi; Youji Idei; Hiroaki Nambu; Kenichi Ohhata; Nadateru Hanta (IEEE J. Solid State Circuits, 1996)

A 1.8-ns access, 550-MHz, 4.5-Mb CMOS SRAM. - Hiroaki Nambu; Kazuo Kanetani; Kaname Yamasaki; Keiichi Higeta; Masami Usami; Yasuhiro Fujimura; Kazumasa Ando; Takeshi Kusunoki; Kunihiko Yamaguchi; Noriyuki Homma (IEEE J. Solid State Circuits, 1998)

Synonym hit RAM - a 500-MHz CMOS SRAM macro with 576-bit parallel comparison and parity check functions. - Takeshi Suzuki; Keiichi Higeta; Yasuhiro Fujimura; Kazumasa Ando; Hiroaki Nambu; Ryo Yamagata; Atsuo Hotta; Kunihiko Yamaguchi (IEEE J. Solid State Circuits, 2000)