Analysis of coupling noise between adjacent bit lines in megabit DRAMs. - Yasuhiro Konishi; Masaki Kumanoya; Hiroyuki Yamasaki; Katsumi Dosaka; Tsutomu Yoshihara (IEEE J. Solid State Circuits, 1989)

A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode. - Yasuhiro Konishi; Katsumi Dosaka; Takahiro Komatsu; Yoshinori Inoue; Masaki Kumanoya; Youichi Tobita; Hideki Genjyo; Masao Nagatomo; Tsutomu Yoshihara (IEEE J. Solid State Circuits, 1990)

A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter. - Masaki Tsukude; Kazutami Arimoto; Hideto Hidaka; Yasuhiro Konishi; Masanori Hayashikoshi; Katsunori Suma; Kazuyasu Fujishima (ITC, 1992)

A 34-ns 16-Mb DRAM with controllable voltage down-converter. - Hideto Hidaka; Kazutami Arimoto; Kazutoshi Hirayama; Masanori Hayashikoshi; Mikio Asakura; Masaki Tsukude; Tsukasa Oishi; Shinji Kawai; Katsuhiro Suma; Yasuhiro Konishi; Koji Tanaka; Wataru Wakamiya; et al. (IEEE J. Solid State Circuits, 1992)

A 100-MHz 4-Mb cache DRAM with fast copy-back scheme. - Katsumi Dosaka; Yasuhiro Konishi; Kouji Hayano; Katsumitsu Himukashi; Akira Yamazaki; Hisashi Iwamoto; Masaki Kumanoya; Hisanori Hamano; Tsutomu Yoshihara (IEEE J. Solid State Circuits, 1992)

Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters. - Masaki Tsukude; Kazutami Arimoto; Hideto Hidaka; Yasuhiro Konishi; Masanori Hayashikoshi; Katsuhiro Suma; Kazuyasu Fujishima (IEEE Des. Test Comput., 1993)

Testing 256k Word x 16 Bit Cache DRAM (CDRAM). - Yasuhiro Konishi; Toshiyuki Ogawa; Masaki Kumanoya (ITC, 1994)

400-MHz random column operating SDRAM techniques with self-skew compensation. - Takeshi Hamamoto; Masaki Tsukude; Kazutami Arimoto; Yasuhiro Konishi; Takayuki Miyamoto; Hideyuki Ozaki; Michihiro Yamada (IEEE J. Solid State Circuits, 1998)

A precharged-capacitor-assisted sensing (PCAS) scheme with novel level controllers for low-power DRAMs. - Takashi Kono; Takeshi Hamamoto; Katsuyoshi Mitsui; Yasuhiro Konishi; Tsutomu Yoshihara; Hideyuki Ozaki (IEEE J. Solid State Circuits, 2000)

A 0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica. - Shigehiro Kuge; Tetsuo Kato; Kiyohiro Furutani; Shigeru Kikuda; Katsuyoshi Mitsui; Takeshi Hamamoto; Jun Setogawa; Kei Hamade; Yuichiro Komiya; Satoshi Kawasaki; Takashi Kono; Teruhiko Amano; et al. (IEEE J. Solid State Circuits, 2000)

A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM. - Takeshi Hamamoto; Kiyohiro Furutani; Takashi Kubo; Satoshi Kawasaki; Hironori Iga; Takashi Kono; Yasuhiro Konishi; Tsutomu Yoshihara (IEEE J. Solid State Circuits, 2004)

Highly Flexible Row and Column Redundancy and Cycle Time Adaptive Read Data Path for Double Data Rate Synchronous Memories. - Kiyohiro Furutani; Takeshi Hamamoto; Takeo Miki; Masaya Nakano; Takashi Kono; Shigeru Kikuda; Yasuhiro Konishi; Tsutomu Yoshihara (IEICE Trans. Electron., 2005)