Power-Minimum Frequency/Voltage Cooperative Management Method for VLSI Processor in Leakage-Dominant Technology Era. - Kentaro Kawakami; Miwako Kanamori; Yasuhiro Morita; Jun Takemura; Masayuki Miyama; Masahiko Yoshimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering. - Hidehiro Fujiwara; Koji Nii; Junichi Miyakoshi; Yuichiro Murachi; Yasuhiro Morita; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISLPED, 2006)

A Feed-Forward Dynamic VDD-VBB-Frequency Management for Low Power Motion Video Compression on 90NM Risc Processor. - Kentaro Kawakami; Miwako Kanamori; Yasuhiro Morita; Jun Takemura; Hideo Ohira; Masayuki Miyama; Masahiko Yoshimoto (Intell. Autom. Soft Comput., 2006)

Vertical Partitioning Method for Secret Sharing Distributed Database System. - Toshiyuki Miyamoto; Yasuhiro Morita; Sadatoshi Kumagai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond. - Yasuhiro Morita; Hidehiro Fujiwara; Hiroki Noguchi; Kentaro Kawakami; Junichi Miyakoshi; Shinji Mikami; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing. - Hiroki Noguchi; Yusuke Iguchi; Hidehiro Fujiwara; Yasuhiro Morita; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISVLSI, 2007)

Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme. - Yasuhiro Morita; Hidehiro Fujiwara; Hiroki Noguchi; Yusuke Iguchi; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes. - Yasuhiro Morita; Hidehiro Fujiwara; Hiroki Noguchi; Yusuke Iguchi; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2007)

Quality of a Bit (QoB): A New Concept in Dependable SRAM. - Hidehiro Fujiwara; Shunsuke Okumura; Yusuke Iguchi; Hiroki Noguchi; Yasuhiro Morita; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISQED, 2008)

A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing. - Hiroki Noguchi; Yusuke Iguchi; Hidehiro Fujiwara; Shunsuke Okumura; Yasuhiro Morita; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2008)

Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering. - Hidehiro Fujiwara; Koji Nii; Hiroki Noguchi; Junichi Miyakoshi; Yuichiro Murachi; Yasuhiro Morita; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Wireless DC voltage transmission using inductive-coupling channelfor highly-parallel wafer-level testing. - Yoichi Yoshida; Koichi Nose; Yoshihiro Nakagawa; Koichiro Noguchi; Yasuhiro Morita; Masamoto Tago; Tadahiro Kuroda; Masayuki Mizuno (ISSCC, 2009)

An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing. - Yoichi Yoshida; Koichi Nose; Yoshihiro Nakagawa; Koichiro Noguchi; Yasuhiro Morita; Masamoto Tago; Masayuki Mizuno; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2010)