A VLSI RISC with 20-MFLOPS peak, 64-bit floating-point unit. - Katsuyuki Kaneko; Tadashi Okamoto; Masaitsu Nakajima; Yasuhiro Nakakura; Satoshi Gokita; Junji Nishikawa; Yuji Tanikawa; Hiroshi Kadota (IEEE J. Solid State Circuits, 1989)

Parallel computer ADENART - its architecture and application. - Hiroshi Kadota; Katsuyuki Kaneko; Ichiro Okabayashi; Tadashi Okamoto; T. Mimura; Yasuhiro Nakakura; Akiyoshi Wakatani; Masaitsu Nakajima; Junji Nishikawa; K. Zaiki; Tatsuo Nogi (ICS, 1991)

OHMEGA: A VLSI Superscalar Processor Architecture for Numerical Applications. - Masaitsu Nakajima; Hiraku Nakano; Yasuhiro Nakakura; Tadahiro Yoshida; Yoshiyuki Goi; Yuji Nakai; Reiji Segawa; Takeshi Kishida; Hiroshi Kadota (ISCA, 1991)

An Accurate, High Speed Implementation of Division by the Quasi-Unity Divisor Method. - Hiraku Nakano; Masaitsu Nakajima; Yasuhiro Nakakura; Tadahiro Yoshida; Yoshiyuki Goi; Yuji Nakai; Reiji Segawa; Takeshi Kishida (IFIP Congress (1), 1992)

An 80-MFLOPS (peak) 64-b microprocessor for parallel computer. - Hiraku Nakano; Masaitsu Nakajima; Yasuhiro Nakakura; Tadahiro Yoshida; Yoshiyuki Goi; Yuji Nakai; Reiji Segawa; Takeshi Kishida; Hiroshi Kadota (IEEE J. Solid State Circuits, 1992)

An Area-Effective Cell-Based Channel Decoder LSI For a Digital Satellite TV Broadcasting. - Takehiro Kamada; Toshihiko Fukuoka; Yuji Nakai; Yoshihiko Fukumoto; Yasuhiro Nakakura; Katsuhiko Ueda; Tomonori Shiomi; Kazuhiro Ota (J. VLSI Signal Process., 1998)