A 40-ns 64-Mb DRAM with 64-b parallel data bus architecture. - Masao Taguchi; Hiroyoshi Tomita; Toshiya Uchida; Yasuhiro Ohnishi; Kimiaki Sato; Taiji Ema; Masaaki Higashitani; Takashi Yabu (IEEE J. Solid State Circuits, 1991)

Construction of pseudorandom permutations. - Yasuhiro Ohnishi; Akira Maruoka (Syst. Comput. Jpn., 1994)

A Low-Cost, High-Speed, and Robust Bin Picking System for Factory Automation Enabled by a Non-stop, Multi-View, and Active Vision Scheme. - Xingdou Fu; Lin Miao; Yasuhiro Ohnishi; Yuki Hasegawa; Masaki Suwa (IROS, 2024)