An integrated multimedia desktop communication and collaboration platform for broadband ISDN: the broadband ISDN group tele-working system. - Tohru Hoshi; Yasuhiro Takahashi; Kenjiro Mori (Comput. Commun. Rev., 1992)

B-ISDN Multimedia Communication and Collaboration Platform Using Advanced Video Workstations to Support Cooperative Work. - Tohru Hoshi; Kenjiro Mori; Yasuhiro Takahashi; Yoshiyuki Nakayama; Takeshi Ishizaki (IEEE J. Sel. Areas Commun., 1992)

An efficient dialogue control method using decision tree-based estimation of out-of-vocabulary word attributes. - Yasuhiro Takahashi; Kohji Dohsaka; Kiyoaki Aikawa (INTERSPEECH, 2002)

On the computational power of constant-depth quantum circuits with gates for addition. - Yasuhiro Takahashi; Yasuhito Kawano; Masahiro Kitagawa (IEEE Congress on Evolutionary Computation, 2003)

Carry Propagation Free Adder/Subtracter Using Adiabatic Dynamic CMOS Logic Circuit Technology. - Yasuhiro Takahashi; Kei-ichi Konta; Kazukiyo Takahashi; Michio Yokoyama; Kazuhiro Shouno; Mitsuru Mizunuma (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

New cost-effective VLSI implementation of multiplierless FIR filter using common subexpression elimination. - Yasuhiro Takahashi; Michio Yokoyama (ISCAS (2), 2005)

A linear-size quantum circuit for addition with no ancillary qubits. - Yasuhiro Takahashi; Noboru Kunihiro (Quantum Inf. Comput., 2005)

2PADCL: Two Phase drive Adiabatic Dynamic CMOS Logic. - Yasuhiro Takahashi; Youhei Fukuta; Toshikazu Sekine; Michio Yokoyama (APCCAS, 2006)

A quantum circuit for shor's factoring algorithm using 2n + 2 qubits. - Yasuhiro Takahashi; Noboru Kunihiro (Quantum Inf. Comput., 2006)

A 70 MHz Multiplierless FIR Hilbert Transformer in 0.35 µm Standard CMOS Library. - Yasuhiro Takahashi; Toshikazu Sekine; Michio Yokoyama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

VLSI Implementation of a 4 x 4-bit Multiplier in a Two Phase Drive Adiabatic Dynamic CMOS Logic. - Yasuhiro Takahashi; Toshikazu Sekine; Michio Yokoyama (IEICE Trans. Electron., 2007)

The quantum fourier transform on a linear nearest neighbor architecture. - Yasuhiro Takahashi; Noboru Kunihiro; Kazuo Ohta (Quantum Inf. Comput., 2007)

A fast quantum circuit for addition with few qubits. - Yasuhiro Takahashi; Noboru Kunihiro (Quantum Inf. Comput., 2008)

4-bit ripple carry adder of two-phase clocked adiabatic static CMOS logic: A comparison with static CMOS. - Nazrul Anuar; Yasuhiro Takahashi; Toshikazu Sekine (ECCTD, 2009)

Fundamental logics based on two phase clocked adiabatic static CMOS logic. - Nazrul Anuar; Yasuhiro Takahashi; Toshikazu Sekine (ICECS, 2009)

A new horizontal and vertical common subexpression elimination method for multiple constant multiplication. - Kazunari Kato; Yasuhiro Takahashi; Toshikazu Sekine (ICECS, 2009)

Two phase clocked adiabatic static CMOS logic. - Nazrul Anuar; Yasuhiro Takahashi; Toshikazu Sekine (SoC, 2009)

Quantum Arithmetic Circuits: A Survey. - Yasuhiro Takahashi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Simple Sets of Measurements for Universal Quantum Computation and Graph State Preparation. - Yasuhiro Takahashi (TQC, 2010)

4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR. - Nazrul Anuar; Yasuhiro Takahashi; Toshikazu Sekine (VLSI-SoC, 2010)

Quantum addition circuits and unbounded fan-out. - Yasuhiro Takahashi; Seiichiro Tani; Noboru Kunihiro (Quantum Inf. Comput., 2010)

Low-power adiabatic SRAM. - Hides Jamima; Yasuhiro Takahashi; Toshikazu Sekine (ISPACS, 2011)

Resistance against power analysis attacks on adiabatic dynamic and adiabatic differential logics for smart card. - Câncio Monteiro; Yasuhiro Takahashi; Toshikazu Sekine (ISPACS, 2011)

Actual implementation of multi domain test: Further reduction of cost of test. - Yasuhiro Takahashi; Akinori Maeda; Mitsuhiro Ogura (ITC, 2011)

Multi Domain Test: Novel test strategy to reduce the Cost of Test. - Yasuhiro Takahashi; Akinori Maeda (VTS, 2011)

Constant-Depth Exact Quantum Circuits for the OR and Threshold Functions - Yasuhiro Takahashi; Seiichiro Tani (CoRR, 2011)

2PCDAL: Two-phase clocking dual-rail adiabatic logic. - Yasuhiro Takahashi; Zhongyu Luo; Toshikazu Sekine; Nazrul Anuar Nayan; Michio Yokoyama (APCCAS, 2012)

A low-power sense amplifier for adiabatic memory using memristor. - Yuki Urata; Yasuhiro Takahashi; Toshikazu Sekine; Nazrul Anuar Nayan (APCCAS, 2012)

Power-saving analysis of adiabatic logic in subthreshold region. - Yasuhiro Takahashi; Toshikazu Sekine; Nazrul Anuar Nayan; Michio Yokoyama (ISPACS, 2012)

LSI implementation of a low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier. - Nazrul Anuar Nayan; Yasuhiro Takahashi; Toshikazu Sekine (Microelectron. J., 2012)

An estimation method for the 3 port S-parameters with 1 port measurements. - Noboru Maeda; Shinji Fukui 002; Toshikazu Sekine; Yasuhiro Takahashi (ECCTD, 2013)

Low power secure CSSAL bit-parallel multiplier over GF(24) in 0.18μm CMOS technology. - Câncio Monteiro; Yasuhiro Takahashi; Toshikazu Sekine (ECCTD, 2013)

DPA resistance of charge-sharing symmetric adiabatic logic. - Câncio Monteiro; Yasuhiro Takahashi; Toshikazu Sekine (ISCAS, 2013)

Robust secure charge-sharing symmetric adiabatic logic against side-channel attacks. - Câncio Monteiro; Yasuhiro Takahashi; Toshikazu Sekine (TSP, 2013)

Charge-sharing symmetric adiabatic logic in countermeasure against power analysis attacks at cell level. - Câncio Monteiro; Yasuhiro Takahashi; Toshikazu Sekine (Microelectron. J., 2013)

Dissemination of UTC(NICT) by Means of QZSS. - Thomas Hobiger; Yasuhiro Takahashi; Maho Nakamura; Tadahiro Gotoh; Shinichi Hama; Takashi Maruyama; Tsutomu Nagatsuma; Hiroyuki Noda; Motohisa Kishimoto; Kaoru Nakayama; Yasuhiro Ohki (IEEE Trans. Instrum. Meas., 2013)

Skew tolerance analysis and layout design of 4×4 multiplier using two phase clocking subthreshold adiabatic logic. - Kazunari Kato; Yasuhiro Takahashi; Toshikazu Sekine (APCCAS, 2014)

Effectiveness of dual-rail CSSAL against power analysis attack under CMOS process variation. - Câncio Monteiro; Yasuhiro Takahashi; Toshikazu Sekine (APCCAS, 2014)

Power dissipation analysis of memristor for low power integrated circuit applications. - Haruki Ogata; Yasuhiro Takahashi; Toshikazu Sekine (APCCAS, 2014)

Two phase clocking subthreshold adiabatic logic. - Kazunari Kato; Yasuhiro Takahashi; Toshikazu Sekine (ISCAS, 2014)

An LSI implementation of a bit-parallel cellular multiplier over GF(24) using secure charge-sharing symmetric adiabatic logic. - Câncio Monteiro; Yasuhiro Takahashi; Toshikazu Sekine (ISCAS, 2014)

Process variation verification of low-power secure CSSAL AES S-box circuit. - Câncio Monteiro; Yasuhiro Takahashi; Toshikazu Sekine (MWSCAS, 2014)

Hardness of classically simulating quantum circuits with unbounded Toffoli and fan-out gates. - Yasuhiro Takahashi; Takeshi Yamazaki; Kazuyuki Tanaka (Quantum Inf. Comput., 2014)

An improved estimation method of 4 port S-parameters with 2 port measurements. - Noboru Maeda; Shinji Fukui 002; Toshikazu Sekine; Yasuhiro Takahashi (ECCTD, 2015)

Power saving analysis of step-down buck converter using adiabatic switching principle. - Rui Manuel de Oliveira Amaral Sarmento; Yasuhiro Takahashi (ISPACS, 2015)

A 4×4-bit multiplier LSI implementation of two phase clocking subthreshold adiabatic logic. - Kazunari Kato; Yasuhiro Takahashi; Toshikazu Sekine (NEWCAS, 2015)

Two phase clocked subthreshold adiabatic logic circuit. - Kazunari Kato; Yasuhiro Takahashi; Toshikazu Sekine (IEICE Electron. Express, 2015)

SPICE model of memristive device using Tukey window function. - Yasuhiro Takahashi; Toshikazu Sekine; Michio Yokoyama (IEICE Electron. Express, 2015)

Low-power secure S-box circuit using charge-sharing symmetric adiabatic logic for advanced encryption standard hardware design. - Câncio Monteiro; Yasuhiro Takahashi; Toshikazu Sekine (IET Circuits Devices Syst., 2015)

Collapse of the Hierarchy of Constant-Depth Exact Quantum Circuits. - Yasuhiro Takahashi; Seiichiro Tani (Comput. Complex., 2016)

Shallow Quantum Circuits with Uninitialized Ancillary Qubits. - Yasuhiro Takahashi; Seiichiro Tani (CoRR, 2016)

Ancilla-driven instantaneous quantum polynomial time circuit for quantum supremacy. - Yuki Takeuchi; Yasuhiro Takahashi (CoRR, 2016)

Commuting quantum circuits with few outputs are unlikely to be classically simulatable. - Yasuhiro Takahashi; Seiichiro Tani; Takeshi Yamazaki; Kazuyuki Tanaka (Quantum Inf. Comput., 2016)

Generalized indirect S-parameter measurement method of n-ports circuit using T-parameter of (m, n)-ports fixture. - Yuya Kojima; Toshikazu Sekine; Yasuhiro Takahashi (ECCTD, 2017)

Low power Adiabatic Logic based on 2PC2AL. - Mei Han; Yasuhiro Takahashi; Toshikazu Sekine (ICICDT, 2017)

Operational amplifier based LC resonant circuit for adiabatic logic. - Yasuhiro Takahashi; Toshikazu Sekine; Mei Han (MIXDES, 2017)

5.6 GHz, 61.7 dBΩ Transimpedance Amplifier Using Active Inductor in Shunt and Series Peaking Techniques. - Takumi Fukuura; Yasuhiro Takahashi (ISPACS, 2018)

Low Power Source Biased Semi-Adiabatic Logic Circuit for IoT Devices. - Câncio Monteiro; Apolinario Maria; Yasuhiro Takahashi (ISPACS, 2018)

A New Adiabatic Logic without Charge Sharing Gate for Cryptographic Devices. - Ryosuke Ohashi; Yasuhiro Takahashi (ISPACS, 2018)

5.3 GHz, 69.6 dBΩ Transimpedance Amplifier with Negative Impedance Converter. - Ryo Tagawa; Yasuhiro Takahashi (ISPACS, 2018)

Design of a CMOS Broadband Transimpedance Amplifier with Floating Active Inductor. - Xiangyu Chen; Yasuhiro Takahashi (ISVLSI, 2019)

Evaluation of Power Analysis Attacks on Cryptographic Circuit Using Adiabatic Logic. - Hiroki Koyasu; Yasuhiro Takahashi (ISVLSI, 2019)

Post-Layout Simulation of Quasi-Adiabatic Logic Based Physical Unclonable Function. - Yasuhiro Takahashi; Hiroki Koyasu; S. Dinesh Kumar; Himanshu Thapliyal (ISVLSI, 2019)

Non-floating and low-power adiabatic logic circuit. - Mei Han; Yasuhiro Takahashi; Toshikazu Sekine (IEICE Electron. Express, 2019)

Current Pass Optimized Symmetric Pass Gate Adiabatic Logic for Cryptographic Circuits. - Hiroki Koyasu; Yasuhiro Takahashi (IPSJ Trans. Syst. LSI Des. Methodol., 2019)

Special Session: An Adiabatic Logic Based Silicon Physical Unclonable Function. - Kohei Ogura; Yasuhiro Takahashi (ICCD, 2020)

Message from the Technical Program Chairs iSES 2020. - Yasuhiro Takahashi; Tosiron Adegbija; Linga Reddy Cenkeramaddi (iSES, 2020)

Efficiently generating ground states is hard for postselected quantum computation. - Yuki Takeuchi; Yasuhiro Takahashi; Seiichiro Tani (CoRR, 2020)

Performance and Security Evaluation of S-Box Using Current-Pass Optimized Symmetric Pass Gate Adiabatic Logic. - Hiroki Koyasu; Yasuhiro Takahashi (SN Comput. Sci., 2020)

Quasi-Adiabatic SRAM Based Silicon Physical Unclonable Function. - Yasuhiro Takahashi; Hiroki Koyasu; S. Dinesh Kumar; Himanshu Thapliyal (SN Comput. Sci., 2020)

A Burst-Mode TIA with Adaptive Response and Stable Operation for in-Vehicle Optical Networks. - Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine; Daisuke Ito; Yasuhiro Takahashi; Makoto Nakamura (ICECS, 2021)

Ultra-Low-Power FinFETs-Based TPCA-PUF Circuit for Secure IoT Devices. - Câncio Monteiro; Yasuhiro Takahashi (Sensors, 2021)

Power of uninitialized qubits in shallow quantum circuits. - Yasuhiro Takahashi; Seiichiro Tani (Theor. Comput. Sci., 2021)

Classically simulating quantum circuits with local depolarizing noise. - Yasuhiro Takahashi; Yuki Takeuchi; Seiichiro Tani (Theor. Comput. Sci., 2021)

Capacitor Under Pad for Small Area Integration of High-Speed Signal-to-Differential Amplifier. - Akira Tsuchiya; Toshiyuki Inoue; Keiji Kishine; Yasuhiro Takahashi; Daisuke Ito; Makoto Nakamura (ICEIC, 2022)

A Burst-Mode TIA with Automatic Power Saving and DC Wander Reduction in 65-nm CMOS. - Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine; Daisuke Ito; Yasuhiro Takahashi; Makoto Nakamura (ICECS 2022, 2022)

A 28-Gb/s VCSEL Driver with Variable Output Impedance in 65-nm CMOS. - Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine; Daisuke Ito; Yasuhiro Takahashi; Makoto Nakamura (MWSCAS, 2022)

A Small-Area Integration of Optical Receiver Using Multi-Layer Inductors and Capacitor-Under-Pad. - Akira Tsuchiya; Toshiyuki Inoue; Keiji Kishine; Yasuhiro Takahashi; Daisuke Ito; Makoto Nakamura (MWSCAS, 2022)

Divide-and-conquer verification method for noisy intermediate-scale quantum computation. - Yuki Takeuchi; Yasuhiro Takahashi; Tomoyuki Morimae; Seiichiro Tani (Quantum, 2022)

High-Speed, Low-Power, and Small-Area Optical Receiver in 65-nm CMOS. - Akira Tsuchiya; Toshiyuki Inoue; Keiji Kishine; Daisuke Ito; Yasuhiro Takahashi; Makoto Nakamura (ASICON, 2023)

A 4×32-Gb/s VCSEL Driver with Adaptive Feedforward Equalization in 65-nm CMOS. - Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine; Daisuke Ito; Yasuhiro Takahashi; Makoto Nakamura (ICECS, 2023)

4-ch 25-Gb/s Small and Low-power VCSEL Driver Circuit with Unbalanced CML in 65-nm CMOS. - Daisuke Ito; Yasuhiro Takahashi; Makoto Nakamura; Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine (ISOCC, 2023)

10Gb/s burst-mode driver circuit with on-chip bias switch for in-Vehicle optical networks. - Daisuke Ito; Yasuhiro Takahashi; Makoto Nakamura; Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine (IEICE Electron. Express, 2023)

Low-power and small-area 4-ch 25-Gb/s transimpedance amplifiers in 65-nm CMOS process. - Yasuhiro Takahashi; Daisuke Ito; Makoto Nakamura; Akira Tsuchiya; Toshiyuki Inoue; Keiji Kishine (IEICE Electron. Express, 2023)

Design of Low-Power 6T Adiabatic PUF Circuit. - Jiaming Liu; Yasuhiro Takahashi (APCCAS, 2024)

Low-power and Small-area Transimpedance Amplifier with Active Inductor in 65 nm CMOS. - Takato Masuda; Yasuhiro Takahashi (APCCAS, 2024)

A Design of PUF Circuit Using Adiabatic Logic. - Shoya Nagata; Yasuhiro Takahashi (APCCAS, 2024)

A 25-Gb/s Active Feedback Transimpedance Amplifier in 65-nm CMOS. - Yasuhiro Takahashi; Daisuke Ito; Makoto Nakamura; Akira Tsuchiya; Toshiyuki Inoue; Keiji Kishine (ICEIC, 2024)

Low-Power, 25-Gb/s Active Voltage Current Feedback Transimpedance Amplifier in 65-nm CMOS. - Koji Tominaga; Yasuhiro Takahashi (ICEIC, 2024)

Power-efficiency estimation of exponential horn driver circuit for low-power optical link. - Daisuke Ito; Masataka Furuta; Yasuhiro Takahashi; Makoto Nakamura (ISOCC, 2024)

A Small-Area and Low-EPB Inductive-Peaking VCSEL Driver for a 65-nm CMOS Chip. - Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine; Daisuke Ito; Yasuhiro Takahashi; Makoto Nakamura (SOCC, 2024)

A burst-mode receiver with quick response and high consecutive identical digit tolerance for advanced intra-vehicle optical networks. - Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine; Daisuke Ito; Yasuhiro Takahashi; Makoto Nakamura (Microelectron. J., 2024)

A 16-Channel Optical Receiver Circuit for a Multicore Fiber-Based Co-Packaged Optics Module in a 65-nm CMOS Chip. - Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine; Yasuhiro Takahashi; Daisuke Ito; Makoto Nakamura (IEEE Trans. Circuits Syst. II Express Briefs, 2024)