250 Mbyte/s synchronous DRAM using a 3-stage-pipelined architecture. - Yasuhiro Takai; Mamoru Nagase; Mamoru Kitamura; Yasuji Koshikawa; Naoyuki Yoshida; Yasuaki Kobayashi; Takashi Obara; Yukio Fukuzo; Hiroshi Watanabe (IEEE J. Solid State Circuits, 1994)

A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme. - Yasuhiro Takai; Mamoru Fujita; Kyoichi Nagata; Satoshi Isa; Shigeyuki Nakazawa; Atsunori Hirobe; Hiroaki Ohkubo; Masato Sakao; Shinichi Horiba; Tadashi Fukase; Yoshihiro Takaishi; Makoto Matsuo; et al. (IEEE J. Solid State Circuits, 2000)

A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer. - Tatsuya Matano; Yasuhiro Takai; Tsugio Takahashi; Yuusuke Sakito; Isamu Fujii; Yoshihiro Takaishi; Hiroki Fujisawa; Shuichi Kubouchi; Seiji Narui; Koji Arai; Makoto Morino; Masayuki Nakamura; et al. (IEEE J. Solid State Circuits, 2003)

1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer. - Hiroki Fujisawa; Masayuki Nakamura; Yasuhiro Takai; Yasuji Koshikawa; Tatsuya Matano; Seiji Narui; Narikazu Usuki; Chiaki Dono; Shinichi Miyatake; Makoto Morino; Koji Arai; Shuichi Kubouchi; et al. (IEEE J. Solid State Circuits, 2005)

Session 17 overview: High-performance DRAM interfaces. - Yasuhiro Takai; James Sung (ISSCC, 2013)

Introduction to the Special Issue on the 2012 IEEE International Solid-State Circuits Conference. - Maurits Ortmanns; Timothy C. Fischer; Uming Ko; Wim Dehaene; Yasuhiro Takai (IEEE J. Solid State Circuits, 2013)