Detailed-Routability of FPGAs with Extremal Switch-Block Structures. - Yasuhiro Takashima; Atsushi Takahashi 001; Yoji Kajitani (ED&TC, 1996)

Self-reforming routing for stochastic search in VLSI interconnection layout. - Yukiko Kubo; Yasuhiro Takashima; Shigetoshi Nakatake; Yoji Kajitani (ASP-DAC, 2000)

Two-dimensional placement method based on divide-and-replacement. - Yasuhiro Takashima; Akira Kaneko; Shinji Sato; Mineo Kaneko (APCCAS (2), 2002)

Abstraction and optimization of consistent floorplanning with pillar block constraints. - Ning Fu; Shigetoshi Nakatake; Yasuhiro Takashima; Yoji Kajitani (ASP-DAC, 2004)

Multi-level placement with circuit schema based clustering in analog IC layouts. - Takashi Nojima; Xiaoke Zhu; Yasuhiro Takashima; Shigetoshi Nakatake; Yoji Kajitani (ASP-DAC, 2004)

A device-level placement with multi-directional convex clustering. - Takashi Nojima; Yasuhiro Takashima; Shigetoshi Nakatake; Yoji Kajitani (ACM Great Lakes Symposium on VLSI, 2004)

A fast algorithm for crosspoint assignment under crosstalk constraints with shielding effects. - Keiji Kida; Xiaoke Zhu; Changwen Zhuang; Yasuhiro Takashima; Shigetoshi Nakatake (ISCAS (4), 2004)

A performance-driven circuit bipartitioning algorithm for multi-FPGA implementation with time-multiplexed I/Os. - Masato Inagi; Yasuhiro Takashima; Yuichi Nakamura 002; Yoji Kajitani (FPT, 2006)

How does partitioning matter for 3D floorplanning? - Tan Yan; Qing Dong; Yasuhiro Takashima; Yoji Kajitani (ACM Great Lakes Symposium on VLSI, 2006)

The Oct-Touched Tile: A New Architecture for Shape-Based Routing. - Ning Fu; Shigetoshi Nakatake; Yasuhiro Takashima; Yoji Kajitani (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

A Theoretical Study on Wire Length Estimation Algorithms for Placement with Opaque Blocks. - Tan Yan; Shuting Li; Yasuhiro Takashima; Hiroshi Murata (ASP-DAC, 2007)

A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os. - Masato Inagi; Yasuhiro Takashima; Yuichi Nakamura 002; Yoji Kajitani (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

A Relocation Method for Circuit Modifications. - Kunihiko Yanagibashi; Yasuhiro Takashima; Yuichi Nakamura 002 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Fast wire length estimation in obstructive block placement. - Shuting Li; Tan Yan; Yasuhiro Takashima; Hiroshi Murata (ICECS, 2008)

ILP-based optimization of time-multiplexed I/O assignment for multi-FPGA systems. - Masato Inagi; Yasuhiro Takashima; Yuichi Nakamura 002; Atsushi Takahashi 001 (ISCAS, 2008)

Post-Silicon Clock-Timing Tuning Based on Statistical Estimation. - Yuko Hashizume; Yasuhiro Takashima; Yuichi Nakamura 002 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems. - Masato Inagi; Yasuhiro Takashima; Yuichi Nakamura 002; Atsushi Takahashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems. - Masato Inagi; Yasuhiro Takashima; Yuichi Nakamura 002 (FPL, 2009)

A 172mm2 32Gb MLC NAND flash memory in 34nm CMOS. - Raymond Zeng; Navneet Chalagalla; Dan Chu; Daniel Elmhurst; Matt Goldman 001; Chris Haid; Atif Huq; Takaaki Ichikawa; Joel Jorgensen; Owen Jungroth; Nishnat Kajla; Ravinder Kajley; et al. (ISSCC, 2009)

Delay analysis of sub-path on fabricated chips by several path-delay tests. - Takanobu Shiki; Yasuhiro Takashima; Yuichi Nakamura 002 (ISCAS, 2010)

Globally Optimal Time-multiplexing of Inter-FPGA Connections for Multi-FPGA Prototyping Systems. - Masato Inagi; Yasuhiro Takashima; Yuichi Nakamura 002 (IPSJ Trans. Syst. LSI Des. Methodol., 2010)

Sub-path delay estimation for reconvergent path. - Seiya Nagatsuka; Yasuhiro Takashima (APCCAS, 2012)

An acceleration method by GPGPU for analytical placement using quasi-Newton method. - Syota Kuwabara; Yukihide Kohira; Yasuhiro Takashima (ASICON, 2013)

An Effective Overlap Removable Objective for Analytical Placement. - Syota Kuwabara; Yukihide Kohira; Yasuhiro Takashima (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Delay estimation method for correlated net delay variations. - Masatsugu Hosoki; Seiya Nagatsuka; Yasuhiro Takashima (APCCAS, 2014)

A randomized algorithm for the fixed-length routing problem. - Tieyuan Pan; Ran Zhang 005; Yasuhiro Takashima; Takahiro Watanabe (APCCAS, 2014)

Analytical placement for rectilinear blocks. - Yasuhiro Takashima (ASP-DAC, 2015)

Inter-FPGA Routing for Partially Time-Multiplexing Inter-FPGA Signals on Multi-FPGA Systems with Various Topologies. - Masato Inagi; Yuichi Nakamura 002; Yasuhiro Takashima; Shin'ichi Wakabayashi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memory. - Tomoharu Tanaka; Mark Helm; Tommaso Vali; Ramin Ghodsi; Koichi Kawai; Jae-Kwan Park; Shigekazu Yamada; Feng Pan; Yuichi Einaga; Ali Ghalam; Toru Tanzawa; Jason Guo; et al. (ISSCC, 2016)

PEVaS: Power and execution-time variation-aware scheduling for MPSoC. - Komei Nomura; Yasuhiro Takashima; Yuichi Nakamura 002 (NEWCAS, 2016)

A multi-functional memory unit with PLA-based reconfigurable decoder. - Nobuyuki Yahiro; Bo Liu 031; Atsushi Nanri; Shigetoshi Nakatake; Yasuhiro Takashima; Gong Chen 002 (ReConFig, 2016)

A Fast MER Enumeration Algorithm for Online Task Placement on Reconfigurable FPGAs. - Tieyuan Pan; Lian Zeng; Yasuhiro Takashima; Takahiro Watanabe (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

An Online Task Placement Algorithm Based on MER Enumeration for Partially Reconfigurable Device. - Tieyuan Pan; Li Zhu; Lian Zeng; Takahiro Watanabe; Yasuhiro Takashima (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Fast Approximate Algorithm for the Single Source Shortest Path with Lazy Update. - Tomohiro Takahashi; Yasuhiro Takashima (NGCAS, 2018)

Task Allocation and Scheduling Optimization in the Heterogeneous Core System. - Ryota Tsuchihashi; Komei Nomura; Yasuhiro Takashima; Yuichi Nakamura 002 (NGCAS, 2018)

Theoretical and Experimental Analysis of Traveling Salesman Walk Problem. - Yasuhiro Takashima; Yuichi Nakamura 002 (APCCAS, 2021)