A shared-well dual-supply-voltage 64-bit ALU. - Yasuhisa Shimazaki; Radu Zlatanovici; Borivoje Nikolic (IEEE J. Solid State Circuits, 2004)

A 4500 MIPS/W, 86 µA Resume-Standby, 11 µA Ultra-Standby Application Processor for 3G Cellular Phones. - Makoto Ishikawa; Tatsuya Kamei; Yuki Kondo; Masanao Yamaoka; Yasuhisa Shimazaki; Motokazu Ozawa; Saneaki Tamaki; Mikio Furuyama; Tadashi Hoshi; Fumio Arakawa; Osamu Nishii; Kenji Hirose; et al. (IEICE Trans. Electron., 2005)

A 300-MHz 25-μA/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor. - Masanao Yamaoka; Yoshihiro Shinozaki; Noriaki Maeda; Yasuhisa Shimazaki; Kei Kato; Shigeru Shimada; Kazumasa Yanagisawa; Kenichi Osada (IEEE J. Solid State Circuits, 2005)

Hierarchical power distribution and power management scheme for a single chip mobile processor. - Toshihiro Hattori; Takahiro Irita; Masayuki Ito; Eiji Yamamoto; Hisashi Kato; Go Sado; Tetsuhiro Yamada; Kunihiko Nishiyama; Hiroshi Yagi; Takao Koike; Yoshihiko Tsuchihashi; Motoki Higashida; et al. (DAC, 2006)

A Power Management Scheme Controlling 20 Power Domains for a Single-Chip Mobile Processor. - Toshihiro Hattori; Takahiro Irita; Masayuki Ito; Eiji Yamamoto; Hisashi Kato; Go Sado; Tetsuhiro Yamada; Kunihiko Nishiyama; Hiroshi Yagi; Takao Koike; Yoshihiko Tsuchihashi; Motoki Higashida; et al. (ISSCC, 2006)

Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor. - Yusuke Kanno; Hiroyuki Mizuno; Yoshihiko Yasu; Kenji Hirose; Yasuhisa Shimazaki; Tadashi Hoshi; Yujiro Miyairi; Toshifumi Ishii; Tetsuya Yamada; Takahiro Irita; Toshihiro Hattori; Kazumasa Yanagisawa; et al. (ISSCC, 2006)

90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique. - Masanao Yamaoka; Noriaki Maeda; Yoshihiro Shinozaki; Yasuhisa Shimazaki; Koji Nii; Shigeru Shimada; Kazumasa Yanagisawa; Takayuki Kawahara (IEEE J. Solid State Circuits, 2006)

Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs. - Yusuke Kanno; Hiroyuki Mizuno; Yoshihiko Yasu; Kenji Hirose; Yasuhisa Shimazaki; Tadashi Hoshi; Yujiro Miyairi; Toshifumi Ishii; Tetsuya Yamada; Takahiro Irita; Toshihiro Hattori; Kazumasa Yanagisawa; et al. (IEEE J. Solid State Circuits, 2007)

65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS. - Masanao Yamaoka; Noriaki Maeda; Yasuhisa Shimazaki; Kenichi Osada (ISSCC, 2008)

A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation. - Shigenobu Komatsu; Masanao Yamaoka; Masao Morimoto; Noriaki Maeda; Yasuhisa Shimazaki; Kenichi Osada (CICC, 2009)

An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM. - Kiichi Niitsu; Yasuhisa Shimazaki; Yasufumi Sugimori; Yoshinori Kohama; Kazutaka Kasuga; Itaru Nonomura; Makoto Saen; Shigenobu Komatsu; Kenichi Osada; Naohiko Irie; Toshihiro Hattori; Atsushi Hasegawa; et al. (ISSCC, 2009)

3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link. - Makoto Saen; Kenichi Osada; Yasuyuki Okuma; Kiichi Niitsu; Yasuhisa Shimazaki; Yasufumi Sugimori; Yoshinori Kohama; Kazutaka Kasuga; Itaru Nonomura; Naohiko Irie; Toshihiro Hattori; Atsushi Hasegawa; et al. (IEEE J. Solid State Circuits, 2010)

A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors. - Yasuhisa Shimazaki; Noriyuki Miura; Tadahiro Kuroda (COOL Chips, 2012)

A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs. - Yuichiro Ishii; Yasumasa Tsukamoto; Koji Nii; Hidehiro Fujiwara; Makoto Yabuuchi; Koji Tanaka; Shinji Tanaka; Yasuhisa Shimazaki (ISSCC, 2012)

A 0.41µA standby leakage 32Kb embedded SRAM with Low-Voltage resume-standby utilizing all digital current comparator in 28nm HKMG CMOS. - Noriaki Maeda; Shigenobu Komatsu; Masao Morimoto; Yasuhisa Shimazaki (VLSIC, 2012)

A 0.41 µA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS. - Noriaki Maeda; Shigenobu Komatsu; Masao Morimoto; Koji Tanaka; Yasumasa Tsukamoto; Koji Nii; Yasuhisa Shimazaki (IEEE J. Solid State Circuits, 2013)

4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10-7 random hardware failures per hour reliability. - Chikafumi Takahashi; Shinichi Shibahara; Kazuki Fukuoka; Jun Matsushima; Yuko Kitaji; Yasuhisa Shimazaki; Hirotaka Hara; Takahiro Irita (ISSCC, 2016)

3.5 A 40nm flash microcontroller with 0.80µs field-oriented-control intelligent motor timer and functional safety system for next-generation EV/HEV. - Hayato Kimura 003; Hideyuki Noda; Hisaaki Watanabe; Takashi Higuchi; Ryosaku Kobayashi; Masayuki Utsuno; Fumitake Takami; Sugako Otani; Masayuki Ito; Yasuhisa Shimazaki; Naoki Yada; Hiroyuki Kondo (ISSCC, 2017)

Session 8 overview: Digital PLLs and security circuits. - Yasuhisa Shimazaki; John Maneatis; Edith Beigné (ISSCC, 2017)

A 16 nm FinFET Heterogeneous Nona-Core SoC Supporting ISO26262 ASIL B Standard. - Shinichi Shibahara; Chikafumi Takahashi; Kazuki Fukuoka; Yuko Kitaji; Takahiro Irita; Hirotaka Hara; Yasuhisa Shimazaki; Jun Matsushima (IEEE J. Solid State Circuits, 2017)

A 28nm 600MHz Automotive Flash Microcontroller with Virtualization-Assisted Processor for Next-Generation Automotive Architecture Complying with ISO26262 ASIL-D. - Sugako Otani; Norimasa Otsuki; Yasufumi Suzuki; Naoto Okumura; Shohei Maeda; Tomonori Yanagita; Takao Koike; Yasuhisa Shimazaki; Masao Ito; Minoru Uemura; Toshihiro Hattori; Tadaaki Yamauchi; et al. (ISSCC, 2019)

A 28-nm Automotive Flash Microcontroller With Virtualization-Assisted Processor Supporting ISO26262 ASIL D. - Hiroyuki Kondo; Yasuhisa Shimazaki; Masao Ito; Minoru Uemura; Toshihiro Hattori; Noriaki Sakamoto; Sugako Otani; Norimasa Otsuki; Yasufumi Suzuki; Naoto Okumura; Shohei Maeda; Tomonori Yanagita; et al. (IEEE J. Solid State Circuits, 2020)

A 33kDMIPS 6.4W Vehicle Communication Gateway Processor Achieving 10Gbps/W Network Routing, 40ms CAN Bus Start-Up and 1.4mW Standby Power. - Kenichi Shimada; Keiichiro Sano; Kazuki Fukuoka; Hiroshi Morita; Masayuki Daito; Tatsuya Kamei; Hiroyuki Hamasaki; Yasuhisa Shimazaki (ISSCC, 2023)