Performance Evaluation of 3-Dimensional MIN with Cache Consistency Maintenance Mechanism. - Yasuki Tanabe; Takashi Midorikawa; Daisuke Shiraishi; Masayoshi Shigeno; Toshihiro Hanawa; Hideharu Amano (PDPTA, 2003)

Design and Evaluation of a Switch Architecture for Multistage Interconnection Network with Temporary Directory. - Masato Sumiyoshi; Takashi Midorikawa; Yasuki Tanabe; Hideharu Amano (PDCS, 2004)

Implementation of ISIS-SimpleScalar. - Toshihiro Hanawa; Toshiya Minai; Yasuki Tanabe; Hideharu Amano (PDPTA, 2005)

The performance of SNAIL-2 (a SSS-MIN connected multiprocessor with cache coherent mechanism). - Takashi Midorikawa; Daisuke Shiraishi; Masayoshi Shigeno; Yasuki Tanabe; Toshihiro Hanawa; Hideharu Amano (Parallel Comput., 2005)

Visconti2 - a heterogeneous multi-core SoC for image-recognition applications. - Masato Uchiyama; Hideho Arakida; Yasuki Tanabe; Tsukasa Ike; Takanori Tamai; Moriyasu Banno (Hot Chips Symposium, 2012)

A 464GOPS 620GOPS/W heterogeneous multi-core SoC for image-recognition applications. - Yasuki Tanabe; Masato Sumiyoshi; Manabu Nishiyama; Itaru Yamazaki; Shinsuke Fujii; Katsuyuki Kimura; Takuma Aoyama; Moriyasu Banno; Hiroo Hayashi; Takashi Miyamori (ISSCC, 2012)

Implementation and evaluation of image recognition algorithm for an intelligent vehicle using heterogeneous multi-core SoC. - Nau Ozaki; Masato Uchiyama; Yasuki Tanabe; Shuichi Miyazaki; Takaaki Sawada; Takanori Tamai; Moriyasu Banno (ASP-DAC, 2015)

Visual co-occurrence network: using context for large-scale object recognition in retail. - Siddharth Advani; Brigid Smith; Yasuki Tanabe; Kevin M. Irick; Matthew Cotter; Jack Sampson; Vijaykrishnan Narayanan (ESTIMedia, 2015)

A scalable architecture for multi-class visual object detection. - Siddharth Advani; Yasuki Tanabe; Kevin M. Irick; Jack Sampson; Vijaykrishnan Narayanan (FPL, 2015)

A Power-Efficient Hybrid Architecture Design for Image Recognition Using CNNs. - Jinhang Choi; Srivatsa Rangachar Srinivasa; Yasuki Tanabe; Jack Sampson; Vijaykrishnan Narayanan (ISVLSI, 2018)

A 20.5TOPS and 217.3GOPS/mm2 Multicore SoC with DNN Accelerator and Image Signal Processor Complying with ISO26262 for Automotive Applications. - Yutaka Yamada; Toru Sano; Yasuki Tanabe; Yutaro Ishigaki; Soichiro Hosoda; Fumihiko Hyuga; Akira Moriya; Ryuji Hada; Atsushi Masuda; Masato Uchiyama; Tomohiro Koizumi; Takanori Tamai; et al. (ISSCC, 2019)

A 20.5 TOPS Multicore SoC With DNN Accelerator and Image Signal Processor for Automotive Applications. - Yutaka Yamada; Masato Uchiyama; Masashi Jobashi; Tomohiro Koizumi; Takanori Tamai; Nobuhiro Sato; Jun Tanabe; Katsuyuki Kimura; Yoshinari Ojima; Ryusuke Murakami; Takashi Yoshikawa; Toru Sano; et al. (IEEE J. Solid State Circuits, 2020)