A New Timing Calibration Method for High Speed Memory Test. - Yasumasa Nishimura; Mitsuhiro Hamada; Y. Hayasaka (ITC, 1984)

Redundancy Test for 1 Mbit DRAM Using Multi-Bit-Test Mode. - Yasumasa Nishimura; Mitsuhiro Hamada; Hideto Hidaka; Hideyuki Ozaki; Kazuyasu Fujishima; Y. Hayasaka (ITC, 1986)

A redundancy test-time reduction technique in 1-Mbit DRAM with a multibit test mode. - Yasumasa Nishimura; Mitsuhiro Hamada; Hideto Hidaka; Hideyuki Ozaki; Kazuyasu Fujishima (IEEE J. Solid State Circuits, 1989)

A 20-ns 4-Mb CMOS SRAM with hierarchical word decoding architecture. - Toshihiko Hirose; Hirotada Kuriyama; Shuji Murakami; Kojiro Yuzuriha; Takao Mukai; Kazuhito Tsutsumi; Yasumasa Nishimura; Yoshio Kohno; Kenji Anami (IEEE J. Solid State Circuits, 1990)

An 8 ns 4 Mb serial access memory. - Hirotada Kuriyama; Toshihiko Hirose; Shuji Murakami; Tomohisa Wada; Kore-aki Fujita; Yasumasa Nishimura; Kenji Anami (IEEE J. Solid State Circuits, 1991)

A 21-mW 4-Mb CMOS SRAM for battery operation. - Shuji Murakami; Kore-aki Fujita; Motomu Ukita; Kazuhito Tsutsumi; Yasuo Inoue; Osamu Sakamoto; Motoi Ashida; Yasumasa Nishimura; Yoshio Kohno; Tadashi Nishimura; Kenji Anami (IEEE J. Solid State Circuits, 1991)

A single-bit-line cross-point cell activation (SCPA) architecture for ultra-low-power SRAM's. - Motomu Ukita; Shuji Murakami; Tadato Yamagata; Hirotada Kuriyama; Yasumasa Nishimura; Kenji Anami (IEEE J. Solid State Circuits, 1993)

A distributed globally replaceable redundancy scheme for sub-half-micron ULSI memories and beyond. - Tadato Yamagata; Hirotoshi Sato; Kore-aki Fujita; Yasumasa Nishimura; Kenji Anami (IEEE J. Solid State Circuits, 1996)

Open architecture tester: what is a key issue of OAT? - Yasumasa Nishimura (ASP-DAC, 2004)