3-D numerical modeling of thermal flow for insulating thin film using surface diffusion. - Masato Fujinaga; I. Tottori; Tatsuya Kunikiyo; Tetsuya Uchida; Norihiko Kotani; Yasumasa Tsukamoto (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications. - Koji Nii; Yasumasa Tsukamoto; Tomoaki Yoshizawa; Susumu Imaoka; Yoshinobu Yamagami; Toshikazu Suzuki; Akinori Shibayama; Hiroshi Makino; Shuhei Iwade (IEEE J. Solid State Circuits, 2004)

Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability. - Yasumasa Tsukamoto; Koji Nii; Susumu Imaoka; Yuji Oda; Shigeki Ohbayashi; Tomoaki Yoshizawa; Hiroshi Makino; Koichiro Ishibashi; Hirofumi Shinohara (ICCAD, 2005)

A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure. - Niichi Itoh; Yasumasa Tsukamoto; Takeshi Shibagaki; Koji Nii; Hidehiro Takata; Hiroshi Makino (ISCAS (1), 2005)

A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die. - Shigeki Ohbayashi; Makoto Yabuuchi; Kazushi Kono; Yuji Oda; Susumu Imaoka; Keiichi Usui; Toshiaki Yonezu; Takeshi Iwamoto; Koji Nii; Yasumasa Tsukamoto; Masashi Arakawa; Takahiro Uchida; et al. (ISSCC, 2007)

A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations. - Makoto Yabuuchi; Koji Nii; Yasumasa Tsukamoto; Shigeki Ohbayashi; Susumu Imaoka; Hiroshi Makino; Yoshinobu Yamagami; Satoshi Ishikura; Toshio Terano; Toshiyuki Oashi; Keiji Hashimoto; Akio Sebe; et al. (ISSCC, 2007)

A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits. - Shigeki Ohbayashi; Makoto Yabuuchi; Koji Nii; Yasumasa Tsukamoto; Susumu Imaoka; Yuji Oda; Tsutomu Yoshihara; Motoshige Igarashi; Masahiko Takeuchi; Hiroshi Kawashima; Yasuo Yamaguchi; Kazuhiro Tsukamoto; et al. (IEEE J. Solid State Circuits, 2007)

A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues. - Satoshi Ishikura; Marefusa Kurumada; Toshio Terano; Yoshinobu Yamagami; Naoki Kotani; Katsuji Satomi; Koji Nii; Makoto Yabuuchi; Yasumasa Tsukamoto; Shigeki Ohbayashi; Toshiyuki Oashi; Hiroshi Makino; et al. (IEEE J. Solid State Circuits, 2008)

A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations. - Koji Nii; Makoto Yabuuchi; Yasumasa Tsukamoto; Shigeki Ohbayashi; Susumu Imaoka; Hiroshi Makino; Yoshinobu Yamagami; Satoshi Ishikura; Toshio Terano; Toshiyuki Oashi; Keiji Hashimoto; Akio Sebe; et al. (IEEE J. Solid State Circuits, 2008)

A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die. - Shigeki Ohbayashi; Makoto Yabuuchi; Kazushi Kono; Yuji Oda; Susumu Imaoka; Keiichi Usui; Toshiaki Yonezu; Takeshi Iwamoto; Koji Nii; Yasumasa Tsukamoto; Masashi Arakawa; Takahiro Uchida; et al. (IEEE J. Solid State Circuits, 2008)

Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access. - Koji Nii; Yasumasa Tsukamoto; Makoto Yabuuchi; Yasuhiro Masuda; Susumu Imaoka; Keiichi Usui; Shigeki Ohbayashi; Hiroshi Makino; Hirofumi Shinohara (IEEE J. Solid State Circuits, 2009)

A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body bias. - Koji Nii; Makoto Yabuuchi; Yasumasa Tsukamoto; Yuuichi Hirano; Toshiaki Iwamatsu; Yuji Kihara (ISSCC, 2010)

Dynamic stability in minimum operating voltage Vmin for single-port and dual-port SRAMs. - Yasumasa Tsukamoto; Takeshi Kida; T. Yamaki; Yuichiro Ishii; Koji Nii; Koji Tanaka; Shinji Tanaka; Yuji Kihara (CICC, 2011)

A dynamic body-biased SRAM with asymmetric halo implant MOSFETs. - Makoto Yabuuchi; Yasumasa Tsukamoto; Hidehiro Fujiwara; Shigeki Tawa; Koji Maekawa; Motoshige Igarashi; Koji Nii (ISLPED, 2011)

A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues. - Yuichiro Ishii; Hidehiro Fujiwara; Shinji Tanaka; Yasumasa Tsukamoto; Koji Nii; Yuji Kihara; Kazumasa Yanagisawa (IEEE J. Solid State Circuits, 2011)

A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues. - Koji Nii; Yasumasa Tsukamoto; Yuichiro Ishii; Makoto Yabuuchi; Hidehiro Fujiwara; Kazuyoshi Okamoto (Asian Test Symposium, 2012)

Optimization of importance sampling Monte Carlo using consecutive mean-shift method and its application to SRAM dynamic stability analysis. - Takeshi Kida; Yasumasa Tsukamoto; Yuji Kihara (ISQED, 2012)

Quasi-Planar Tri-gate (QPT) bulk CMOS technology for single-port SRAM application. - Yasumasa Tsukamoto; Makoto Yabuuchi; Hidehiro Fujiwara; Koji Nii; Changhwan Shin; Tsu-Jae King Liu (ISQED, 2012)

A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs. - Yuichiro Ishii; Yasumasa Tsukamoto; Koji Nii; Hidehiro Fujiwara; Makoto Yabuuchi; Koji Tanaka; Shinji Tanaka; Yasuhisa Shimazaki (ISSCC, 2012)

A stable chip-ID generating physical uncloneable function using random address errors in SRAM. - Hidehiro Fujiwara; Makoto Yabuuchi; Yasumasa Tsukamoto; Hirofumi Nakano; Toru Owada; Hiroyuki Kawai; Koji Nii (SoCC, 2012)

A 28nm high density 1R/1W 8T-SRAM macro with screening circuitry against read disturb failure. - Makoto Yabuuchi; Hidehiro Fujiwara; Yasumasa Tsukamoto; Miki Tanaka; Shinji Tanaka; Koji Nii (CICC, 2013)

A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry. - Koji Nii; Makoto Yabuuchi; Hidehiro Fujiwara; Yasumasa Tsukamoto; Yuichiro Ishii; Tetsuya Matsumura; Yoshio Matsuda (ISQED, 2013)

A 0.41 µA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS. - Noriaki Maeda; Shigenobu Komatsu; Masao Morimoto; Koji Tanaka; Yasumasa Tsukamoto; Koji Nii; Yasuhisa Shimazaki (IEEE J. Solid State Circuits, 2013)

13.3 20nm High-density single-port and dual-port SRAMs with wordline-voltage-adjustment system for read/write assists. - Makoto Yabuuchi; Yasumasa Tsukamoto; Masao Morimoto; Miki Tanaka; Koji Nii (ISSCC, 2014)

A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitline. - Shinji Tanaka; Yuichiro Ishii; Makoto Yabuuchi; Toshiaki Sano; Koji Tanaka; Yasumasa Tsukamoto; Koji Nii; Hirotoshi Sato (VLSIC, 2014)

28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique. - Yukiko Umemoto; Koji Nii; Jiro Ishikawa; Makoto Yabuuchi; Kazuyoshi Okamoto; Yasumasa Tsukamoto; Shinji Tanaka; Koji Tanaka; Tetsuya Matsumura; Kazutaka Mori; Kazumasa Yanagisawa (IEEE Trans. Very Large Scale Integr. Syst., 2014)

1.8 Mbit/mm2 ternary-CAM macro with 484 ps search access time in 16 nm Fin-FET bulk CMOS technology. - Yasumasa Tsukamoto; Masao Morimoto; Makoto Yabuuchi; Miki Tanaka; Koji Nii (VLSIC, 2015)

A 5.92-Mb/mm2 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry. - Yuichiro Ishii; Makoto Yabuuchi; Yohei Sawada; Masao Morimoto; Yasumasa Tsukamoto; Yuta Yoshida; Ken Shibata; Toshiaki Sano; Shinji Tanaka; Koji Nii (A-SSCC, 2016)

NBTI/PBTI separated BTI monitor with 4.2x sensitivity by standard cell based unbalanced ring oscillator. - Mitsuhiko Igarashi; Yoshio Takazawa; Yasumasa Tsukamoto; Kan Takeuchi; Koji Shibutani (A-SSCC, 2017)

A Fully Standard-Cell Based On-Chip BTI and HCI Monitor with 6.2x BTI sensitivity and 3.6x HCI sensitivity at 7 nm Fin-FET Process. - Mitsuhiko Igarashi; Yuuki Uchida; Yoshio Takazawa; Yasumasa Tsukamoto; Koji Shibutani; Koji Nii (A-SSCC, 2018)

Study of impact of BTI's local layout effect including recovery effect on various standard-cells in 10nm FinFET. - Mitsuhiko Igarashi; Yuuki Uchida; Yoshio Takazawa; Yasumasa Tsukamoto; Koji Shibutani; Koji Nii (IRPS, 2018)

A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures. - Makoto Yabuuchi; Yasumasa Tsukamoto; Hidehiro Fujiwara; Miki Tanaka; Shinji Tanaka; Koji Nii (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Study of Local BTI Variation and its Impact on Logic Circuit and SRAM in 7 nm Fin-FET Process. - Mitsuhiko Igarashi; Yuuki Uchida; Yoshio Takazawa; Makoto Yabuuchi; Yasumasa Tsukamoto; Koji Shibutani (IRPS, 2019)

A 7nm Fin-FET 4.04-Mb/mm2 TCAM with Improved Electromigration Reliability Using Far-Side Driving Scheme and Self-Adjust Reference Match-Line Amplifier. - Makoto Yabuuchi; Masao Morimoto; Yasumasa Tsukamoto; Shinji Tanaka (VLSI Circuits, 2020)

An Analysis of Local BTI Variation with Ring-Oscillator in Advanced Processes and Its Impact on Logic Circuit and SRAM. - Mitsuhiko Igarashi; Yuuki Uchida; Yoshio Takazawa; Makoto Yabuuchi; Yasumasa Tsukamoto; Koji Shibutani; Kazutoshi Kobayashi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021)

Leakage Current Fluctuation of On/Off-State Stress in 3 nm Process and its Guard-band Compensation. - Mitsuhiko Igarashi; Yuuki Uchida; Keiichiro Iwamoto; Yoshio Takazawa; Yasumasa Tsukamoto (IRPS, 2025)