A macro analysis of soft errors in static RAMs. - Yasunobu Nakase; Kenji Anami; Tohru Shiomi; Atsushi Ohba; Shinpei Kayano (IEEE J. Solid State Circuits, 1988)

A 2-ns 16K bipolar ECL RAM with reduced word-line voltage swing. - Yasunobu Nakase; Kakutaro Suda; Koichiro Mashiko; Tatsuhiko Ikeda; Shinpei Kayano (IEEE J. Solid State Circuits, 1991)

A 8.8-ns 54 54-Bit Multiplier Using New Redundant Binary Architecture. - Hiroshi Makino; Yasunobu Nakase; Hirofumi Shinohara (ICCD, 1993)

A BiCMOS wired-OR logic. - Yasunobu Nakase; Hiroaki Suzuki; Hiroshi Makino; Hirofumi Shinohara; Koichiro Mashiko (IEEE J. Solid State Circuits, 1995)

An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture. - Hiroshi Makino; Yasunobu Nakase; Hiroaki Suzuki; Hiroyuki Morinaka; Hirofumi Shinohara; Koichiro Mashiko (IEEE J. Solid State Circuits, 1996)

A 286 MHz 64-b floating point multiplier with enhanced CG operation. - Hiroshi Makino; Hiroaki Suzuki; Hiroyuki Morinaka; Yasunobu Nakase; Koichiro Mashiko; Tadashi Sumi (IEEE J. Solid State Circuits, 1996)

Leading-zero anticipatory logic for high-speed floating point addition. - Hiroaki Suzuki; Hiroyuki Morinaka; Hiroshi Makino; Yasunobu Nakase; Koichiro Mashiko; Tadashi Sumi (IEEE J. Solid State Circuits, 1996)

Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply]. - Vojin G. Oklobdzija; Hiroaki Suzuki; Hiroyuki Morinaka; Hiroshi Makino; Yasunobu Nakase; Koichiro Mashiko; Tadashi Sumi (IEEE J. Solid State Circuits, 1997)

Authors Reply. - Hiroaki Suzuki; Hiroyuki Morinaka; Hiroshi Makino; Yasunobu Nakase; Koichiro Mashiko (IEEE J. Solid State Circuits, 1997)

Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface. - Yasunobu Nakase; Yoshikazu Morooka; David J. Perlman; Daniel J. Kolor; Jae-Myoung Choi; Hyun J. Shin; Tsutomu Yoshimura; Naoya Watanabe; Yoshio Matsuda; Masaki Kumanoya; Michihiro Yamada (IEEE J. Solid State Circuits, 1999)

A 600-MHz 54×54-bit multiplier with rectangular-styled Wallace tree. - Niichi Itoh; Yuka Naemura; Hiroshi Makino; Yasunobu Nakase; Tsutomu Yoshihara; Yasutaka Horiba (IEEE J. Solid State Circuits, 2001)

0.8V start-up 92% efficiency on-chip boost DC-DC converters for battery operation micro-computers. - Yasunobu Nakase; Shinichi Hirose; Toru Goda; Kehui Hu; Hiroshi Onoda; Yasuhiro Ido; Hiroyuki Kondo; Wei Kong; Wei Zhang; Tsukasa Oishi; Shintaro Mori; Toru Shimizu (A-SSCC, 2011)

A 0.5V start-up 87% efficiency 0.75mm2 on-chip feed-forward single-inductor dual-output (SIDO) boost DC-DC converter for battery and solar cell operation sensor network micro-computer integration. - Yasunobu Nakase; Shinichi Hirose; Hiroshi Onoda; Yasuhiro Ido; Yoshiaki Shimizu; Tsukasa Oishi; Toshio Kumamoto; Toru Shimizu (CICC, 2012)

On-Chip Single-Inductor Dual-Output DC-DC Boost Converter Having Off-Chip Power Transistor Drive and Micro-Computer Controlled MPPT Modes. - Yasunobu Nakase; Yasuhiro Ido; Tsukasa Oishi; Toru Shimizu (IEICE Trans. Electron., 2013)

0.5 V Start-Up 87% Efficiency 0.75 mm2 On-Chip Feed-Forward Single-Inductor Dual-Output (SIDO) Boost DC-DC Converter for Battery and Solar Cell Operation Sensor Network Micro-Computer Integration. - Yasunobu Nakase; Shinichi Hirose; Hiroshi Onoda; Yasuhiro Ido; Yoshiaki Shimizu; Tsukasa Oishi; Toshio Kumamoto; Toru Shimizu (IEEE J. Solid State Circuits, 2013)

A low power NoC router using the marching memory through type. - Ryota Yasudo; Takahiro Kagami; Hideharu Amano; Yasunobu Nakase; Masashi Watanabe; Tsukasa Oishi; Toru Shimizu; Tadao Nakamura (COOL Chips, 2014)

Design of a low power NoC router using Marching Memory Through type. - Ryota Yasudo; Takahiro Kagami; Hideharu Amano; Yasunobu Nakase; Masashi Watanabe; Tsukasa Oishi; Toru Shimizu; Tadao Nakamura (NOCS, 2014)