A 1.296-to-5.184Gb/s Transceiver with 2.4mW/(Gb/s) Burst-mode CDR using Dual-Edge Injection-Locked Oscillator. - Kenichi Maruko; Tatsuya Sugioka; Hiroaki Hayashi; Zhiwei Zhou; Yasunori Tsukuda; Yuki Yagishita; Hironobu Konishi; Toshikyuki Ogata; Hisashi Owa; Taichi Niki; Kenji Konda; Masahiro Sato; et al. (ISSCC, 2010)

A Stacked CMOS Image Sensor With Array-Parallel ADC Architecture. - Tomohiro Takahashi; Yuichi Kaji; Yasunori Tsukuda; Shinichiro Futami; Katsuhiko Hanzawa; Takahito Yamauchi; Ping Wah Wong; Frederick T. Brady; Phil Holden; Thomas Ayers; Kyohei Mizuta; Susumu Ohki; et al. (IEEE J. Solid State Circuits, 2018)