A Static Load Partitioning Method based on Execution Profile for Committed Choice Languages. - Yasuo Hidaka; Hanpei Koike; Jun'ichi Tatemura; Hidehiko Tanaka (ISLP, 1991)

Multiple Threads in Cyclic Register Windows. - Yasuo Hidaka; Hanpei Koike; Hidehiko Tanaka (ISCA, 1993)

Architecture of parallel management kernel for PIE64. - Yasuo Hidaka; Hanpei Koike; Hidehiko Tanaka (Future Gener. Comput. Syst., 1994)

Design Consideration of 6.25 Gbps Signaling for High-Performance Server. - Jian Hong Jiang; Weixin Gai; Akira Hattori; Yasuo Hidaka; Takeshi Horie; Yoichi Koyanagi; Hideki Osone (ASP-DAC, 2007)

A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer. - Yasuo Hidaka; Weixin Gai; Akira Hattori; Takeshi Horie; Jian Jiang; Kouichi Kanda; Yoichi Koyanagi; Satoshi Matsubara; Hideki Osone (ISSCC, 2007)

A 4-channel 10.3Gb/s backplane transceiver macro with 35dB equalizer and sign-based zero-forcing adaptive control. - Yasuo Hidaka; Weixin Gai; Takeshi Horie; Jian Hong Jiang; Yoichi Koyanagi; Hideki Osone (ISSCC, 2009)

A 4-Channel 1.25-10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control. - Yasuo Hidaka; Weixin Gai; Takeshi Horie; Jian Hong Jiang; Yoichi Koyanagi; Hideki Osone (IEEE J. Solid State Circuits, 2009)

A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel. - Yasuo Hidaka; Takeshi Horie; Yoichi Koyanagi; Takashi Miyoshi; Hideki Osone; Samir Parikh; Subodh M. Reddy; Toshiyuki Shibuya; Yasushi Umezawa; William W. Walker (ISSCC, 2011)

A 10Gb/s 10mW 2-tap reconfigurable pre-emphasis transmitter in 65nm LP CMOS. - Yue Lu 007; Kwangmo Jung; Yasuo Hidaka; Elad Alon (CICC, 2012)

32Gb/s 28nm CMOS time-interleaved transmitter compatible with NRZ receiver with DFE. - Yuuki Ogata; Yasuo Hidaka; Yoichi Koyanagi; Sadanori Akiya; Yuji Terao; Kosuke Suzuki; Keisuke Kashiwa; Masanobu Suzuki; Hirotaka Tamura (ISSCC, 2013)

A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS. - Samir Parikh; Tony Kao; Yasuo Hidaka; Jian Jiang; Asako Toda; Scott McLeod; William W. Walker; Yoichi Koyanagi; Toshiyuki Shibuya; Jun Yamada (ISSCC, 2013)

Design and Analysis of Energy-Efficient Reconfigurable Pre-Emphasis Voltage-Mode Transmitters. - Yue Lu 007; Kwangmo Jung; Yasuo Hidaka; Elad Alon (IEEE J. Solid State Circuits, 2013)