A Kanji Recognition Method which detects Writing Errors. - Tetsuji Morishita; Masahiko Ooura; Yasuo Ishii (Int. J. Pattern Recognit. Artif. Intell., 1988)

Fused Two-Level Branch Prediction with Ahead Calculation. - Yasuo Ishii (J. Instr. Level Parallelism, 2007)

Access map pattern matching for data cache prefetch. - Yasuo Ishii; Mary Inaba; Kei Hiraki (ICS, 2009)

Triple Line-Based Playout for Go - An Accelerator for Monte Carlo Go. - Kenichi Koizumi; Mary Inaba; Kei Hiraki; Yasuo Ishii; Takefumi Miyoshi; Kazuki Yoshizoe (ReConFig, 2009)

Access Map Pattern Matching for High Performance Data Cache Prefetch. - Yasuo Ishii; Mary Inaba; Kei Hiraki (J. Instr. Level Parallelism, 2011)

Unified memory optimizing architecture: memory subsystem control with a unified predictor. - Yasuo Ishii; Mary Inaba; Kei Hiraki (ICS, 2012)

A hybrid method to improve forecasting accuracy utilizing genetic algorithm and its application to stock market price data (J-REIT: Residential type). - Yasuo Ishii; Kazuhiro Takeyasu (SCIS&ISIS, 2014)

Multivariate Analysis on a Questionnaire Investigation for the Rare Sugars. - Yasuo Ishii; Hiromasa Takeyasu; Daisuke Takeyasu; Kazuhiro Takeyasu (SCIS&ISIS, 2016)

Rebasing Instruction Prefetching: An Industry Perspective. - Yasuo Ishii; Jaekyu Lee; Krishnendra Nathella; Dam Sunwoo (IEEE Comput. Archit. Lett., 2020)

The Arm Neoverse N1 Platform: Building Blocks for the Next-Gen Cloud-to-Edge Infrastructure SoC. - Andrea Pellegrini; Ashok Kumar Tummala; Jamshed Jalal; Mark Werkheiser; Anitha Kona; Nigel Stephens; Magnus Bruce; Yasuo Ishii; Joseph Pusdesris; Abhishek Raja; Chris Abernathy; Jinson Koppanalil; et al. (IEEE Micro, 2020)

Securing Branch Predictors with Two-Level Encryption. - Jaekyu Lee; Yasuo Ishii; Dam Sunwoo (ACM Trans. Archit. Code Optim., 2020)

Re-establishing Fetch-Directed Instruction Prefetching: An Industry Perspective. - Yasuo Ishii; Jaekyu Lee; Krishnendra Nathella; Dam Sunwoo (ISPASS, 2021)