Analysis and synthesis of speech based on spectral transform linear predictive method. - Hynek Hermansky; Hiroya Fujisaki; Yasuo Sato (ICASSP, 1983)

Automatic recognition of spoken words from a large vocabulary using syllable templates. - Hiroya Fujisaki; Keikichi Hirose; Tomohiro Inoue; Yasuo Sato (ICASSP, 1984)

Spectral envelope sampling and interpolation in linear predictive analysis of speech. - Hynek Hermansky; Hiroya Fujisaki; Yasuo Sato (ICASSP, 1984)

Connected word recognition by overlap and split of reference patterns and its performance evaluation tests. - Koji Tajima; Mitsuo Komura; Yasuo Sato (ICASSP, 1986)

Timing- and Constraint-Oriented Placement for Interconnected LSIs in Mainframe Design. - Yasushi Ogawa; Tsutomu Itoh; Yoshio Miki; Tatsuki Ishii; Yasuo Sato; Reiji Toyoshima (DAC, 1991)

A Snapshot Algorithm for Distributed Mobile Systems. - Yasuo Sato; Michiko Inoue; Toshimitsu Masuzawa; Hideo Fujiwara (ICDCS, 1996)

A BIST approach for very deep sub-micron (VDSM) defects. - Yasuo Sato; Toyohito Ikeya; Michinobu Nakao; Takaharu Nagumo (ITC, 2000)

Test Generation for Multiple-Threshold Gate-Delay Fault Model. - Michinobu Nakao; Yoshikazu Kiyoshige; Kazumi Hatayama; Yasuo Sato; Takaharu Nagumo (Asian Test Symposium, 2001)

A Practical Logic BIST for ASIC Designs. - Yasuo Sato; Motoyuki Sato; Koki Tsutsumida; Toyohito Ikeya; Masatoshi Kawashima (Asian Test Symposium, 2001)

An Approach to Improve the Resolution of Defect-Based Diagnosis. - Iwao Yamazaki; Hiroki Yamanaka; Toshio Ikeda; Masahiro Takakura; Yasuo Sato (Asian Test Symposium, 2001)

An evaluation of defect-oriented test: WELL-controlled low voltage test. - Yasuo Sato; Masaki Kohno; Toshio Ikeda; Iwao Yamazaki; Masato Hamamoto (ITC, 2001)

At-Speed Built-in Test for Logic Circuits with Multiple Clocks. - Kazumi Hatayama; Michinobu Nakao; Yasuo Sato (Asian Test Symposium, 2002)

Application of High-Quality Built-In Test to Industrial Designs. - Kazumi Hatayama; Michinobu Nakao; Yoshikazu Kiyoshige; Koichiro Natsume; Yasuo Sato; Takaharu Nagumo (ITC, 2002)

A Persistent Diagnostic Technique for Unstable Defects. - Yasuo Sato; Iwao Yamazaki; Hiroki Yamanaka; Toshio Ikeda; Masahiro Takakura (ITC, 2002)

DFT timing design methodology for at-speed BIST. - Yasuo Sato; Motoyuki Sato; Koki Tsutsumida; Masatoshi Kawashima; Kazumi Hatayama; Kazuyuki Nomoto (ASP-DAC, 2003)

DFT Timing Design Methodology for Logic BIST. - Yasuo Sato; Motoyuki Sato; Koki Tsutsumida; Kazumi Hatayama; Kazuyuki Nomoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Technique to Diagnose Open Defects that Takes Coupling Effects into Consideration. - Yasuo Sato; Iwao Yamazaki; Hiroki Yamanaka; Toshio Ikeda; Masahiro Takakura; Kazuhiko Iwasaki (IEICE Trans. Inf. Syst., 2004)

Evaluation of the statistical delay quality model. - Yasuo Sato; Shuji Hamada; Toshiyuki Maeda; Atsuo Takatori; Seiji Kajihara (ASP-DAC, 2005)

Path delay test compaction with process variation tolerance. - Seiji Kajihara; Masayasu Fukunaga; Xiaoqing Wen; Toshiyuki Maeda; Shuji Hamada; Yasuo Sato (DAC, 2005)

Invisible delay quality - SDQM model lights up what could not be seen. - Yasuo Sato; Shuji Hamada; Toshiyuki Maeda; Atsuo Takatori; Yasuyuki Nozuyama; Seiji Kajihara (ITC, 2005)

A dynamic test compaction procedure for high-quality path delay testing. - Masayasu Fukunaga; Seiji Kajihara; Xiaoqing Wen; Toshiyuki Maeda; Shuji Hamada; Yasuo Sato (ASP-DAC, 2006)

At-Speed Testing with Timing Exceptions and Constraints-Case Studies. - Dhiraj Goswami; Kun-Han Tsai; Mark Kassab; Takeo Kobayashi; Janusz Rajski; Bruce Swanson; Darryl Walters; Yasuo Sato; Toshiharu Asaka; Takashi Aikyo (ATS, 2006)

Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects. - Xijiang Lin; Kun-Han Tsai; Chen Wang 014; Mark Kassab; Janusz Rajski; Takeo Kobayashi; Randy Klingenberg; Yasuo Sato; Shuji Hamada; Takashi Aikyo (ATS, 2006)

Defect Diagnosis - Reasoning Methodology. - Yasuo Sato; Kazushi Sugiura; Reisuke Shimoda; Yutaka Yoshizawa; Kenji Norimatsu; Masaru Sanada (ATS, 2006)

Not all Delay Tests Are the Same - SDQL Model Shows True-Time. - Anis Uzzaman; Mick Tegethoff; Bibo Li; Kevin McCauley; Shuji Hamada; Yasuo Sato (ATS, 2006)

Effective Post-BIST Fault Diagnosis for Multiple Faults. - Hiroshi Takahashi; Shuhei Kadoyama; Yoshinobu Higami; Yuzo Takamatsu; Koji Yamazaki; Takashi Aikyo; Yasuo Sato (DFT, 2006)

Recognition of Sensitized Longest Paths in Transition Delay Test. - Shuji Hamada; Toshiyuki Maeda; Atsuo Takatori; Yasuyuki Noduyama; Yasuo Sato (ITC, 2006)

A Framework of High-quality Transition Fault ATPG for Scan Circuits. - Seiji Kajihara; Shohei Morishima; Akane Takuma; Xiaoqing Wen; Toshiyuki Maeda; Shuji Hamada; Yasuo Sato (ITC, 2006)

A Statistical Quality Model for Delay Testing. - Yasuo Sato; Shuji Hamada; Toshiyuki Maeda; Atsuo Takatori; Seiji Kajihara (IEICE Trans. Electron., 2006)

Next Generation Test, Diagnostics and Yield Challenges for EDA, ATE, IP and Fab - A Perspective from All Sides. - Yasuharu Kohiyama; C. P. Ravikumar; Yasuo Sato; Laung-Terng Wang; Yervant Zorian (ATS, 2007)

Post-BIST Fault Diagnosis for Multiple Faults. - Hiroshi Takahashi; Yoshinobu Higami; Shuhei Kadoyama; Yuzo Takamatsu; Koji Yamazaki; Takashi Aikyo; Yasuo Sato (IEICE Trans. Inf. Syst., 2008)

Circuit Failure Prediction by Field Test - A New Task of Testing. - Yasuo Sato (DFT, 2010)

On estimation of NBTI-Induced delay degradation. - Mitsumasa Noda; Seiji Kajihara; Yasuo Sato; Kohei Miyase; Xiaoqing Wen; Yukiya Miura (ETS, 2010)

Aging test strategy and adaptive test scheduling for SoC failure prediction. - Hyunbean Yi; Tomokazu Yoneda; Michiko Inoue; Yasuo Sato; Seiji Kajihara; Hideo Fujiwara (IOLTS, 2010)

Thermal-uniformity-aware X-filling to reduce temperature-induced delay variation for accurate at-speed testing. - Tomokazu Yoneda; Michiko Inoue; Yasuo Sato; Hideo Fujiwara (VTS, 2010)

On Delay Test Quality for Test Cubes. - Shinji Oku; Seiji Kajihara; Yasuo Sato; Kohei Miyase; Xiaoqing Wen (IPSJ Trans. Syst. LSI Des. Methodol., 2010)

Multi-cycle Test with Partial Observation on Scan-Based BIST Structure. - Yasuo Sato; Hisato Yamaguchi; Makoto Matsuzono; Seiji Kajihara (Asian Test Symposium, 2011)

Genetic algorithm based approach for segmented testing. - Xiaoxin Fan; Sudhakar M. Reddy; Senling Wang; Seiji Kajihara; Yasuo Sato (DSN Workshops, 2011)

Temperature-Variation-Aware Test Pattern Optimization. - Tomokazu Yoneda; Makoto Nakao; Michiko Inoue; Yasuo Sato; Hideo Fujiwara (ETS, 2011)

Special session: Multifaceted approaches for field reliability. - Yasuo Sato (VTS, 2011)

Low Power BIST for Scan-Shift and Capture Power. - Yasuo Sato; Senling Wang; Takaaki Kato; Kohei Miyase; Seiji Kajihara (Asian Test Symposium, 2012)

A Scan-Out Power Reduction Method for Multi-cycle BIST. - Senling Wang; Yasuo Sato; Kohei Miyase; Seiji Kajihara (Asian Test Symposium, 2012)

On-chip temperature and voltage measurement for field testing. - Yukiya Miura; Yasuo Sato; Yousuke Miyake; Seiji Kajihara (ETS, 2012)

DART: Dependable VLSI test architecture and its implementation. - Yasuo Sato; Seiji Kajihara; Tomokazu Yoneda; Kazumi Hatayama; Michiko Inoue; Yukiya Miura; Satosni Untake; Takumi Hasegawa; Motoyuki Sato; Kotaro Shimamura (ITC, 2012)

A Failure Prediction Strategy for Transistor Aging. - Hyunbean Yi; Tomokazu Yoneda; Michiko Inoue; Yasuo Sato; Seiji Kajihara; Hideo Fujiwara (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A Stochastic Model for NBTI-Induced LSI Degradation in Field. - Yasuo Sato; Seiji Kajihara (Asian Test Symposium, 2013)

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST. - Akihiro Tomita; Xiaoqing Wen; Yasuo Sato; Seiji Kajihara; Patrick Girard 001; Mohammad Tehranipoor; Laung-Terng Wang (Asian Test Symposium, 2013)

Scan-Out Power Reduction for Logic BIST. - Senling Wang; Yasuo Sato; Seiji Kajihara; Kohei Miyase (IEICE Trans. Inf. Syst., 2013)

An On-Chip Digital Environment Monitor for Field Test. - Seiji Kajihara; Yousuke Miyake; Yasuo Sato; Yukiya Miura (ATS, 2014)

Temperature and Voltage Estimation Using Ring-Oscillator-Based Monitor for Field Test. - Yousuke Miyake; Yasuo Sato; Seiji Kajihara; Yukiya Miura (ATS, 2014)

Reduction of NBTI-Induced Degradation on Ring Oscillators in FPGA. - Yasuo Sato; Masafumi Monden; Yousuke Miyake; Seiji Kajihara (PRDC, 2014)

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST. - Akihiro Tomita; Xiaoqing Wen; Yasuo Sato; Seiji Kajihara; Kohei Miyase; Stefan Holst; Patrick Girard 001; Mohammad Tehranipoor; Laung-Terng Wang (IEICE Trans. Inf. Syst., 2014)

An ECC-based memory architecture with online self-repair capabilities for reliability enhancement. - Gian Mayuga; Yuta Yamato; Tomokazu Yoneda; Michiko Inoue; Yasuo Sato (ETS, 2015)

Physical Power Evaluation of Low Power Logic-BIST Scheme Using Test Element Group Chip. - Senling Wang; Yasuo Sato; Seiji Kajihara; Hiroshi Takahashi (J. Low Power Electron., 2015)

A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST. - Takaaki Kato; Senling Wang; Yasuo Sato; Seiji Kajihara; Xiaoqing Wen (ATS, 2016)

Reliability enhancement of embedded memory with combination of aging-aware adaptive in-field self-repair and ECC. - Gian Mayuga; Yuta Yamato; Tomokazu Yoneda; Yasuo Sato; Michiko Inoue (ETS, 2016)

Reliability-Enhanced ECC-Based Memory Architecture Using In-Field Self-Repair. - Gian Mayuga; Yuta Yamato; Tomokazu Yoneda; Yasuo Sato; Michiko Inoue (IEICE Trans. Inf. Syst., 2016)

Temperature and Voltage Measurement for Field Test Using an Aging-Tolerant Monitor. - Yousuke Miyake; Yasuo Sato; Seiji Kajihara; Yukiya Miura (IEEE Trans. Very Large Scale Integr. Syst., 2016)

On the effects of real time and contiguous measurement with a digital temperature and voltage sensor. - Yousuke Miyake; Yasuo Sato; Seiji Kajihara (ITC-Asia, 2017)

On Flip-Flop Selection for Multi-cycle Scan Test with Partial Observation in Logic BIST. - Shigeyuki Oshima; Takaaki Kato; Senling Wang; Yasuo Sato; Seiji Kajihara (ATS, 2018)

Good Die Prediction Modelling from Limited Test Items. - Takeru Nishimi; Yasuo Sato; Seiji Kajihara; Yoshiyuki Nakamura (ITC-Asia, 2018)

A Selection Method of Ring Oscillators for An On-Chip Digital Temperature And Voltage Sensor. - Yousuke Miyake; Yasuo Sato; Seiji Kajihara (ITC-Asia, 2019)

On-Chip Delay Measurement for In-Field Test of FPGAs. - Yousuke Miyake; Yasuo Sato; Seiji Kajihara (PRDC, 2019)

Highly Reliable Memory Architecture Using Adaptive Combination of Proactive Aging-Aware In-Field Self-Repair and ECC. - Gian Mayuga; Yasuo Sato; Michiko Inoue (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips. - Takaaki Kato; Senling Wang; Yasuo Sato; Seiji Kajihara; Xiaoqing Wen (IEEE Trans. Emerg. Top. Comput., 2020)