Low-Latency Superscalar and Small-Code-Size Microcontroller Core for Automotive, Industrial, and PC-Peripheral Applications. - Yasuo Sugure; Seiji Takeuchi; Yuichi Abe; Hiromichi Yamada; Kazuya Hirayanagi; Akihiko Tomita; Kesami Hagiwara; Takeshi Kataoka; Takanori Shimura (IEICE Trans. Electron., 2006)

Model-based fault injection for failure effect analysis - Evaluation of dependable SRAM for vehicle control units. - Yohei Nakata; Yasuhiro Ito; Yasuo Sugure; Shigeru Oho; Yusuke Takeuchi; Shunsuke Okumura; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (DSN Workshops, 2011)

A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM. - Go Matsukawa; Yohei Nakata; Yuta Kimi; Yasuo Sugure; Masafumi Shimozawa; Shigeru Oho; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ARCS Workshops, 2014)

A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme. - Go Matsukawa; Yohei Nakata; Yasuo Sugure; Shigeru Oho; Yuta Kimi; Masafumi Shimozawa; Shuhei Yoshida; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2015)