Silicon Single-Electron Devices and Their Applications. - Yasuo Takahashi; Akira Fujiwara; Yukinori Ono; Katsumi Murase (ISMVL, 2000)

Experimental and Simulation Studies of Single-Electron-Transistor-Based Multiple-Valued Logic. - Hiroshi Inokawa; Yasuo Takahashi (ISMVL, 2003)

A Single-Electron-Transistor Logic Gate Family and Its Application - Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode Logic. - Katsuhiko Degawa; Takafumi Aoki; Tatsuo Higuchi 001; Hiroshi Inokawa; Yasuo Takahashi (ISMVL, 2004)

A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions. - Hiroshi Inokawa; Yasuo Takahashi; Katsuhiko Degawa; Takafumi Aoki; Tatsuo Higuchi 001 (ISMVL, 2004)

A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors. - Katsuhiko Degawa; Takafumi Aoki; Hiroshi Inokawa; Tatsuo Higuchi 001; Yasuo Takahashi (ISMVL, 2005)

A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors. - Katsuhiko Degawa; Takafumi Aoki; Tatsuo Higuchi 001; Hiroshi Inokawa; Katsuhiko Nishiguchi; Yasuo Takahashi (ISMVL, 2006)

Transfer and Detection of Single Electrons Using Metal-Oxide-Semiconductor Field-Effect Transistors. - Wancheng Zhang; Katsuhiko Nishiguchi; Yukinori Ono; Akira Fujiwara; Hiroshi Yamaguchi; Hiroshi Inokawa; Yasuo Takahashi; Nan-Jian Wu (IEICE Trans. Electron., 2007)

Design of a Two-Bit-Per-Cell Content-Addressable Memory Using Single-Electron Transistors. - Katsuhiko Degawa; Takafumi Aoki; Tatsuo Higuchi 001; Hiroshi Inokawa; Yasuo Takahashi (J. Multiple Valued Log. Soft Comput., 2007)

Full Adder Operation Based on Si Nanodot Array Device with Multiple Inputs and Outputs. - Takuya Kaizawa; Mingyu Jo; Masashi Arita; Akira Fujiwara; Kenji Yamazaki; Yukinori Ono; Hiroshi Inokawa; Yasuo Takahashi (Int. J. Nanotechnol. Mol. Comput., 2009)

Anomalous microstructure formed at the interface between copper ribbon and tin-deposited copper plate by ultrasonic bonding. - Masakatsu Maeda; Takaaki Sato; Naoto Inoue; Daisuke Yagi; Yasuo Takahashi (Microelectron. Reliab., 2011)

Effect of Arrangement of Input Gates on Logic Switching Characteristics of Nanodot Array Device. - Mingu Jo; Yuki Kato; Masashi Arita; Yukinori Ono; Akira Fujiwara; Hiroshi Inokawa; Yasuo Takahashi; Jung-Bum Choi (IEICE Trans. Electron., 2012)

Brownian Circuits: Designs. - Jia Lee; Ferdinand Peper; Sorin Dan Cotofana; Makoto Naruse; Motoichi Ohtsu; Tadashi Kawazoe; Yasuo Takahashi; Tetsuya Shimokawa; Laszlo B. Kish; Tohru Kubota (Int. J. Unconv. Comput., 2016)

Associative search using pseudo-analog memristors. - Mika Laiho; Mika Grönroos; Jussi H. Poikonen; Eero Lehtonen; Reon Katsumura; Atsushi T.-Fukuchi; Masashi Arita; Yasuo Takahashi (ISCAS, 2017)