A 110-MHz/1-Mb synchronous TagRAM. - Yasuo Unekawa; Tsuguo Kobayashi; Tsukasa Shirotori; Yukihiro Fujimoto; Takayoshi Shimazawa; Kazutaka Nogami; Takehiko Nakao; Kazukiro Sawada; Masataka Matsui; Takayasu Sakurai; Man Kit Tang; William A. Huffman (IEEE J. Solid State Circuits, 1994)

Shared data line technique for doubling the data transfer rate per pin of differential interfaces. - Fumitoshi Hatori; Shouhei Kousai; Yasuo Unekawa (CICC, 2001)

A single-chip 802.11a MAC/PHY with a 32-b RISC processor. - Toshio Fujisawa; Jun Hasegawa; Koji Tsuchie; Tatsuo Shiozawa; Tetsuya Fujita; Toshitada Saito; Yasuo Unekawa (IEEE J. Solid State Circuits, 2003)

A 7uW deep-sleep, ultra low-power WLAN baseband LSI for mobile applications. - Daisuke Taki; Tatsuo Shiozawa; Kuniaki Ito; Youichiro Shiba; Kouji Horisaki; Hirotsugu Kajihara; Toshiyuki Yamagishi; Masahiro Sekiya; Akira Yamaga; Tetsuya Fujita; Hiroyuki Hara; Masanori Kuwahara; et al. (COOL Chips, 2011)

A multimodal wireless baseband core using a coarse-grained dynamic reconfigurable processor. - Hideki Yamada; Toshiyuki Yamagishi; Tomoya Suzuki; Kuniaki Ito; Koji Horisaki; Tom Vander Aa; Toshio Fujisawa; Liesbet Van der Perre; Yasuo Unekawa (COOL Chips, 2011)

High-Throughput, Low-Power Software-Defined Radio Using Reconfigurable Processors. - Tomoya Suzuki; Hideki Yamada; Toshiyuki Yamagishi; Daisuke Takeda; Koji Horisaki; Tom Vander Aa; Toshio Fujisawa; Liesbet Van der Perre; Yasuo Unekawa (IEEE Micro, 2011)

An area-efficient, standard-cell based on-chip NMOS and PMOS performance monitor for process variability compensation. - Toshiyuki Yamagishi; Tatsuo Shiozawa; Koji Horisaki; Hiroyuki Hara; Yasuo Unekawa (COOL Chips, 2012)

A -70dBm-sensitivity 522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX transceiver for TransferJet™ SoC in 65nm CMOS. - Daisuke Miyashita; Kenichi Agawa; Hirotsugu Kajihara; Kenichi Sami; Masaomi Iwanaga; Yosuke Ogasawara; Tomohiko Ito; Daisuke Kurose; Naotaka Koide; Toru Hashimoto; Hiroki Sakurai; Takafumi Yamaji; et al. (VLSIC, 2012)

A 10.4pJ/b (32, 8) LDPC decoder with time-domain analog and digital mixed-signal processing. - Daisuke Miyashita; Ryo Yamaki; Kazunori Hashiyoshi; Hiroyuki Kobayashi; Shouhei Kousai; Yukihito Oowaki; Yasuo Unekawa (ISSCC, 2013)

A -70 dBm-Sensitivity 522 Mbps 0.19 nJ/bit-TX 0.43 nJ/bit-RX Transceiver for TransferJetTM SoC in 65 nm CMOS. - Daisuke Miyashita; Kenichi Agawa; Hirotsugu Kajihara; Kenichi Sami; Ichiro Seto; Ryuichi Fujimoto; Yasuo Unekawa (IEICE Trans. Electron., 2013)

A Standard-Cell Based On-Chip NMOS and PMOS Performance Monitor for Process Variability Compensation. - Toshiyuki Yamagishi; Tatsuo Shiozawa; Koji Horisaki; Hiroyuki Hara; Yasuo Unekawa (IEICE Trans. Electron., 2013)

4.1 A 3-phase digitally controlled DC-DC converter with 88% ripple reduced 1-cycle phase adding/dropping scheme and 28% power saving CT/DT hybrid current control. - Chen Kong Teh; Atsushi Suzuki; Manabu Yamada; Mototsugu Hamada; Yasuo Unekawa (ISSCC, 2014)

19.3 66.3KIOPS-random-read 690MB/s-sequential-read universal Flash storage device controller with unified memory extension. - Konosuke Watanabe; Kenichiro Yoshii; Nobuhiro Kondo; Ken-ichi Maeda; Toshio Fujisawa; Junji Wadatsumi; Daisuke Miyashita; Shouhei Kousai; Yasuo Unekawa; Shinsuke Fujii; Takuma Aoyama; Takayuki Tamura; et al. (ISSCC, 2014)

3D-integrated, low-height, small module design techniques for 4.48GHz, 560MHz-bandwidth TransferJet™ transceiver. - Kenichi Agawa; Ichiro Seto; Akihiko Happoya; Yoshihiro Iida; Yusuke Imaizumi; Motochika Okano; Daigo Suzuki; Yuichi Sato; Masaomi Iwanaga; Kazumi Sato; Satoshi Arai; Noriaki Uchida; et al. (RWS, 2014)

An LDPC Decoder With Time-Domain Analog and Digital Mixed-Signal Processing. - Daisuke Miyashita; Ryo Yamaki; Kazunori Hashiyoshi; Hiroyuki Kobayashi; Shouhei Kousai; Yukihito Oowaki; Yasuo Unekawa (IEEE J. Solid State Circuits, 2014)

A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit. - Fumihiko Tachibana; Osamu Hirabayashi; Yasuhisa Takeyama; Miyako Shizuno; Atsushi Kawasumi; Keiichi Kushida; Azuma Suzuki; Yusuke Niki; Shinichi Sasaki; Tomoaki Yabe; Yasuo Unekawa (IEEE J. Solid State Circuits, 2014)

An 802.11ax 4×4 spectrum-efficient WLAN AP transceiver SoC supporting 1024QAM with frequency-dependent IQ calibration and integrated interference analyzer. - Shusuke Kawai; Hiromitsu Aoyama; Rui Ito; Yutaka Shimizu; Mitsuyuki Ashida; Asuka Maki; Tomohiko Takeuchi; Hiroyuki Kobayashi; Go Urakawa; Hiroaki Hoshino; Shigehito Saigusa; Kazushi Koyama; et al. (ISSCC, 2018)