An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology. - Katsuhiro Suma; Takahiro Tsuruda; Hideto Hidaka; Takahisa Eimori; Toshiyuki Oashi; Yasuo Yamaguchi; Toshiaki Iwamatsu; Masakazu Hirose; Fukashi Morishita; Kazutarni Arimoto; Kazuyasu Fujishima; Yasuo Inoue; et al. (IEEE J. Solid State Circuits, 1994)

A 1-V 46-ns 16-Mb SOI-DRAM with body control technique. - Ken'ichi Shimomura; Hiroki Shimano; Narumi Sakashita; Fumihiro Okuda; Toshiyuki Oashi; Yasuo Yamaguchi; Takahisa Eimori; Masahide Inuishi; Kazutami Arimoto; Shigeto Maegawa; Yasuo Inoue; Shinji Komori; et al. (IEEE J. Solid State Circuits, 1997)

A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits. - Shigeki Ohbayashi; Makoto Yabuuchi; Koji Nii; Yasumasa Tsukamoto; Susumu Imaoka; Yuji Oda; Tsutomu Yoshihara; Motoshige Igarashi; Masahiko Takeuchi; Hiroshi Kawashima; Yasuo Yamaguchi; Kazuhiro Tsukamoto; et al. (IEEE J. Solid State Circuits, 2007)

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology. - Koichiro Ishibashi; Nobuyuki Sugii; Kimiyoshi Usami; Hideharu Amano; Kazutoshi Kobayashi; Cong-Kha Pham; Hideki Makiyama; Yoshiki Yamamoto; Hirofumi Shinohara; Toshiaki Iwamatsu; Yasuo Yamaguchi; Hidekazu Oda; et al. (COOL Chips, 2014)

SOTB (Silicon on Thin Buried Oxide): More than Moore technology for IoT and Automotive. - Takumi Hasegawa; Yoshiki Yamamoto; Hideki Makiyama; Hiroki Shinkawata; Shiro Kamohara; Yasuo Yamaguchi (ICICDT, 2017)