A low power SRAM using auto-backgate-controlled MT-CMOS. - Koji Nii; Hiroshi Makino; Yoshiki Tsujihashi; Chikayoshi Morishima; Yasushi Hayakawa; Hiroyuki Nunogami; Takahiko Arakawa; Hisanori Hamano (ISLPED, 1998)

A 6Gb/s RX Equalizer Adapted Using Direct Measurement of the Equalizer Output Amplitude. - H. Uchiki; Y. Ota; M. Tani; Yasushi Hayakawa; Katsushi Asahina (ISSCC, 2008)

An 80Gb/s dependable communication SoC with PCI express I/F and 8 CPUs. - Sugako Otani; Hiroyuki Kondo; Itaru Nonomura; Atsuyuki Ikeya; Minoru Uemura; Yasushi Hayakawa; Takeshi Oshita; Satoshi Kaneko; Katsushi Asahina; Kazutami Arimoto; Shin'ichi Miura; Toshihiro Hanawa; et al. (ISSCC, 2011)