A 25-ns 4-Mbit CMOS SRAM with dynamic bit-line loads. - Fumio Miyaji; Yasushi Matsuyama; Yoshikazu Kanaishi; Katsunori Seno; Takashi Emori; Yoshiaki Hagiwara (IEEE J. Solid State Circuits, 1989)

A multibit test trigger circuit for megabit SRAMs. - Fumio Miyaji; Takashi Emori; Yasushi Matsuyama; Yoshikazu Kanaishi; Katsunori Seno; Yoshiaki Hagiwara (IEEE J. Solid State Circuits, 1990)

A Moodle-Based E-Syllabus for Institutional Research: Curriculum Mapping and Competency Assessments. - Yoshikazu Asada; Hitoaki Okazaki; Naohiro Sata; Hiroshi Kawahira; Shinichi Yamamoto; Yasushi Matsuyama (IIAI-AAI, 2020)