An Interactive Simulation System for structured logic design - ISS. - Takeshi Sakai; Yoshiyuki Tsuchida; Hiroto Yasuura; Yasushi Ooi; Yoshitsugu Ono; Hiroshi Kano; Shinji Kimura; Shuzo Yajima (DAC, 1982)

An encoder/decoder chip set for the MPEG video standard. - Ichiro Tamitani; Mutsumi Ohta; Yasushi Ooi; Akio Yoshida; Mamoru Nomura; Hitoshi Koyama; Takao Nishitani (ICASSP, 1992)

Fault-tolerant architecture in a cache memory control LSI. - Yasushi Ooi; Masahiko Kashimura; Hidenori Takeuchi; Eiji Kawamura (IEEE J. Solid State Circuits, 1992)

An MPEG-2 encoder architecture based on a single-chip dedicated LSI with a control MPU. - Yasushi Ooi; Osamu Ohnishi; Yutaka Yokoyama; Yoichi Katayama; Masayuki Mizuno; Masakazu Yamashina; Hideo Takano; Naoya Hayashi; Ichiro Tamitani (ICASSP, 1997)

A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking. - Masayuki Mizuno; Yasushi Ooi; Naoya Hayashi; Junichi Goto; Masatoshi Hozumi; Koichiro Furuta; Atsufumi Shibayama; Yoetsu Nakazawa; Osamu Ohnishi; Shu-Yu Zhu; Yutaka Yokoyama; Yoichi Katayama; et al. (IEEE J. Solid State Circuits, 1997)

A Scene-Adaptive One-Pass Variable Bit Rate Video Coding Method for Storage Media. - Yutaka Yokoyama; Yasushi Ooi (ICIP (3), 1999)

A Block Processing Unit in a Single-Chip MPEG-2 Video Encoder LSI. - Yoichi Katayama; Toshiaki Kitsuki; Yasushi Ooi (J. VLSI Signal Process., 1999)