A DSP line equalizer VLSI for TCM digital subscriber-line transmission. - Hideki Ando; Masao Nakaya; Hiroki Hona; Ihuo Iizuka; Yasutaka Horiba (IEEE J. Solid State Circuits, 1988)

An SOI structure for flash A/D converter. - Toshio Kumamoto; Masao Nakaya; Shigeru Kusunoki; Tadashi Nishimura; Nobuharu Yazawa; Yoichi Akasaka; Yasutaka Horiba (IEEE J. Solid State Circuits, 1988)

A 24-b 50-ns digital image signal processor. - Shin-ichi Nakagawa; Hideyuki Terane; Tetsuya Matsumura; Hiroshi Segawa; Masahiko Yoshimoto; Hirofumi Shinohara; Shuichi Kato; Masahiro Hatanaka; Hideo Ohira; Yoshiaki Kato; Mamoru Iwatsuki; Kinya Tabuchi; et al. (IEEE J. Solid State Circuits, 1990)

A flexible multiport RAM compiler for data path. - Hirofumi Shinohara; Noriaki Matsumoto; Kumiko Fujimori; Yoshiki Tsujihashi; Hiroomi Nakao; Shuichi Kato; Yasutaka Horiba; Akiharu Tada (IEEE J. Solid State Circuits, 1991)

The D30V/MPEG multimedia processor. - Hidehiro Takata; Tetsuya Watanabe; Tetsuo Nakajima; Takashi Takagaki; Hisakazu Sato; Atsushi Mohri; Akira Yamada 005; Toshiki Kanamoto; Yoshio Matsuda; Shuhei Iwade; Yasutaka Horiba (IEEE Micro, 1999)

A 600-MHz 54×54-bit multiplier with rectangular-styled Wallace tree. - Niichi Itoh; Yuka Naemura; Hiroshi Makino; Yasunobu Nakase; Tsutomu Yoshihara; Yasutaka Horiba (IEEE J. Solid State Circuits, 2001)

A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures. - Toshiki Kanamoto; Tetsuya Watanabe; Mitsutoshi Shirota; Masayuki Terai; Tatsuya Kunikiyo; Kiyoshi Ishikawa; Yoshihide Ajioka; Yasutaka Horiba (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design. - Takayuki Gyohten; Fukashi Morishita; Isamu Hayashi; Mako Okamoto; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Yasutaka Horiba (IEICE Trans. Electron., 2006)