Multigrain parallel processing on compiler cooperative chip multiprocessor. - Keiji Kimura; Yasutaka Wada; Hirofumi Nakano; Takeshi Kodaka; Jun Shirako; Kazuhisa Ishizaka; Hironori Kasahara (Interaction between Compilers and Computer Architectures, 2005)

Performance Evaluation of Compiler Controlled Power Saving Scheme. - Jun Shirako; Munehiro Yoshida; Naoto Oshiyama; Yasutaka Wada; Hirofumi Nakano; Hiroaki Shikano; Keiji Kimura; Hironori Kasahara (ISHPC, 2005)

Compiler Control Power Saving Scheme for Multi Core Processors. - Jun Shirako; Naoto Oshiyama; Yasutaka Wada; Hiroaki Shikano; Keiji Kimura; Hironori Kasahara (LCPC, 2005)

Power-Aware Compiler Controllable Chip Multiprocessor. - Hiroaki Shikano; Jun Shirako; Yasutaka Wada; Keiji Kimura; Hironori Kasahara (PACT, 2007)

Software-cooperative power-efficient heterogeneous multi-core for media processing. - Hiroaki Shikano; Masaki Ito; Kunio Uchiyama; Toshihiko Odaka; Akihiro Hayashi; Takeshi Masuura; Masayoshi Mase; Jun Shirako; Yasutaka Wada; Keiji Kimura; Hironori Kasahara (ASP-DAC, 2008)

Parallelization with Automatic Parallelizing Compiler Generating Consumer Electronics Multicore API. - Takamichi Miyamoto; Saori Asaka; Hiroki Mikami; Masayoshi Mase; Yasutaka Wada; Hirofumi Nakano; Keiji Kimura; Hironori Kasahara (ISPA, 2008)

Heterogeneous Multi-Core Architecture That Enables 54x AAC-LC Stereo Encoding. - Hiroaki Shikano; Masaki Ito; Masafumi Onouchi; Takashi Todaka; Takanobu Tsunoda; Tomoyuki Kodama; Kunio Uchiyama; Toshihiko Odaka; Tatsuya Kamei; Ei Nagahama; Manabu Kusaoke; Yusuke Nitta; et al. (IEEE J. Solid State Circuits, 2008)

A 45nm 37.3GOPS/W heterogeneous multi-core SoC. - Yoichi Yuyama; Masayuki Ito; Yoshikazu Kiyoshige; Yusuke Nitta; Shigezumi Matsui; Osamu Nishii; Atsushi Hasegawa; Makoto Ishikawa; Tetsuya Yamada; Junichi Miyakoshi; Koichi Terada; Tohru Nojiri; et al. (ISSCC, 2010)

Parallelizing Compiler Framework and API for Power Reduction and Software Productivity of Real-Time Heterogeneous Multicores. - Akihiro Hayashi; Yasutaka Wada; Takeshi Watanabe; Takeshi Sekiguchi; Masayoshi Mase; Jun Shirako; Keiji Kimura; Hironori Kasahara (LCPC, 2010)

Efficient Parallel Implementations of Controlled Optimization of Traffic Phases. - Sameh Samra; Ahmed El-Mahdy 002; Walid Gomaa 001; Yasutaka Wada; Amin A. Shoukry (ICA3PP (1), 2011)

A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core. - Osamu Nishii; Yoichi Yuyama; Masayuki Ito; Yoshikazu Kiyoshige; Yusuke Nitta; Makoto Ishikawa; Tetsuya Yamada; Junichi Miyakoshi; Yasutaka Wada; Keiji Kimura; Hironori Kasahara; Hideo Maejima (IEICE Trans. Electron., 2011)

A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture. - Yasutaka Wada; Akihiro Hayashi; Takeshi Masuura; Jun Shirako; Hirofumi Nakano; Hiroaki Shikano; Keiji Kimura; Hironori Kasahara (Trans. High Perform. Embed. Archit. Compil., 2011)

A Scalable Multiplier for Arbitrary Large Numbers Supporting Homomorphic Encryption. - Ghada Y. Abozaid; Ahmed El-Mahdy 002; Yasutaka Wada (DSD, 2013)

A Linear-Time and Space Algorithm for Optimal Traffic Signal Durations at an Intersection. - Sameh Samra; Ahmed El-Mahdy 002; Yasutaka Wada (CoRR, 2013)

Coarse Grain Task Parallelization of Earthquake Simulator GMS Using OSCAR Compiler on Various Cc-NUMA Servers. - Mamoru Shimaoka; Yasutaka Wada; Keiji Kimura; Hironori Kasahara (LCPC, 2015)

Analyzing and mitigating the impact of manufacturing variability in power-constrained supercomputing. - Yuichi Inadomi; Tapasya Patki; Koji Inoue; Mutsumi Aoyagi; Barry Rountree; Martin Schulz 001; David K. Lowenthal; Yasutaka Wada; Keiichiro Fukazawa; Masatsugu Ueda; Masaaki Kondo; Ikuo Miyoshi (SC, 2015)

Towards FHE in Embedded Systems: A Preliminary Codesign Space Exploration of a HW/SW Very Large Multiplier. - Ghada Y. Abozaid; Arnaud Tisserand; Ahmed El-Mahdy 002; Yasutaka Wada (IEEE Embed. Syst. Lett., 2015)

A Linear Time and Space Algorithm for Optimal Traffic-Signal Duration at an Intersection. - Sameh Samra; Ahmed El-Mahdy 002; Yasutaka Wada (IEEE Trans. Intell. Transp. Syst., 2015)

Development of an FPGA Controlled "Mini-Car" Toward Autonomous Driving. - Musashi Aoto; Yasutaka Wada; Yousuke Numata (FPT, 2018)

A Power Management Framework with Simple DSL for Automatic Power-Performance Optimization on Power-Constrained HPC Systems. - Yasutaka Wada; Yuan He 002; Thang Cao; Masaaki Kondo (SCFA, 2018)

Towards the Improvement of Training Efficiency and Image Recognition Accuracy for an FPGA Controlled Mini-Car by Offloading Neural Network Training. - Musashi Aoto; Moe Mitsugi; Takumi Momose; Yasutaka Wada (FPT, 2019)

An FPGA-Based Image Recognition with Remote Update Functions for Autonomous Driving on "ad-refkit". - Hyuga Hashimoto; Ryo Naka; Yasutaka Wada (FPT, 2021)

Mitigating Process Variations with Cooperative Tuning for Performance and Power through a Simple DSL. - Yunjiao Ma; Yuan He 002; Yasutaka Wada; Wenchao Luo; Ryuichi Sakamoto; Masaaki Kondo (CANDAR (Workshops), 2021)

Secure Image Inference Using Pairwise Activation Functions. - Jonas T. Agyepong; Mostafa Soliman; Yasutaka Wada; Keiji Kimura; Ahmed El-Mahdy 002 (IEEE Access, 2021)

Efficient and Precise Profiling, Modeling and Management on Power and Performance for Power Constrained HPC Systems. - Yuan He 002; Yasutaka Wada; Wenchao Luo; Ryuichi Sakamoto; Guanqin Pan; Thang Cao; Masaaki Kondo (IEICE Trans. Electron., 2021)

Performance Evaluation of Data Transfer API for Rank Level Approximate Computing on HPC Systems. - Yoshiyuki Morie; Yasutaka Wada; Ryohei Kobayashi 001; Ryuichi Sakamoto (IPDPS Workshops, 2022)

Data Transfer API and its Performance Model for Rank-Level Approximate Computing on HPC Systems. - Yoshiyuki Morie; Yasutaka Wada; Ryohei Kobayashi 001; Ryuichi Sakamoto (Int. J. Netw. Comput., 2023)

Special Issue on Cool Chips. - Ryusuke Egawa; Yasutaka Wada (IEEE Micro, 2023)

Foreword. - Ryusuke Egawa; Yasutaka Wada (IEICE Trans. Electron., 2023)

Ideal Parametrisation Estimation for Variational Quantum Circuit Classifiers Using Machine Learning. - Mostafa Fathi; Walid Gomaa 001; Yasutaka Wada; Keiji Kimura; Kazunori Ueda; Ahmed El-Mahdy 002 (QCE, 2024)