CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example]. - Takeshi Kumaki; Yasuto Kuroda; Tetsushi Koide; Hans Jürgen Mattausch; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Kazunori Saito (ISCAS (5), 2005)

Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine. - Takeshi Kumaki; Tetsushi Koide; Hans Jürgen Mattausch; Yasuto Kuroda; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Kazunori Saito (ISCAS, 2007)

Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor. - Takeshi Kumaki; Masakatsu Ishizaki; Tetsushi Koide; Hans Jürgen Mattausch; Yasuto Kuroda; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Kazunori Saito (IEICE Trans. Inf. Syst., 2007)

Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer. - Takeshi Kumaki; Yasuto Kuroda; Masakatsu Ishizaki; Tetsushi Koide; Hans Jürgen Mattausch; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Kazunori Saito (IEICE Trans. Inf. Syst., 2007)

Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor. - Takeshi Kumaki; Masakatsu Ishizaki; Tetsushi Koide; Hans Jürgen Mattausch; Yasuto Kuroda; Takayuki Gyohten; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Kazunori Saito (IEICE Trans. Electron., 2008)

Hardware implementation of fast forwarding engine using standard memory and dedicated circuit. - Kazuya Zaitsu; Koji Yamamoto 002; Yasuto Kuroda; Kazunari Inoue; Shingo Ata; Ikuo Oka (ICECS, 2010)

Deterministic High Density Packet-Buffer System for Low Cost Network Systems. - Hisashi Iwamoto; Yuji Yano; Yasuto Kuroda; Koji Yamamoto 002; Shingo Ata; Kazunari Inoue (AINA, 2012)

A 200Msps, 0.6W eDRAM-based search engine applying full-route capacity dedicated FIB application. - Yasuto Kuroda; Yuji Yano; Hisashi Iwamoto; Koji Yamamoto 002; Kazunari Inoue; Masahiro Suzuki (CICC, 2012)

A slice structure using the management of network traffic prediction for green IT. - Yuji Yano; Hisashi Iwamoto; Yasuto Kuroda; Shiro Ohtani; Shingo Ata; Kazunari Inoue (HPSR, 2012)

FPS-RAM: Fast Prefix Search RAM-Based Hardware for Forwarding Engine. - Kazuya Zaitsu; Koji Yamamoto 002; Yasuto Kuroda; Kazunari Inoue; Shingo Ata; Ikuo Oka (IEICE Trans. Commun., 2012)

2D Sliced Packet Buffer with traffic volume and buffer occupancy adaptation for power saving. - Kenzo Okuda; Shingo Ata; Yasuto Kuroda; Yuji Yano; Hisashi Iwamoto; Kazunari Inoue; Ikuo Oka (CCNC, 2013)

Deterministic Packet Buffer System with Multi FIFO Queues for the Advanced QoS. - Hisashi Iwamoto; Yuji Yano; Yasuto Kuroda; Koji Yamamoto 002; Shingo Ata; Kazunari Inoue (IEICE Trans. Commun., 2013)

A 250 Msps, 0.5 W eDRAM-Based Search Engine Dedicated Low Power FIB Application. - Hisashi Iwamoto; Yuji Yano; Yasuto Kuroda; Koji Yamamoto 002; Kazunari Inoue; Ikuo Oka (IEICE Trans. Electron., 2013)

A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS. - Isamu Hayashi; Teruhiko Amano; Naoya Watanabe; Yuji Yano; Yasuto Kuroda; M. Shirata; Katsumi Dosaka; Koji Nii; Hideyuki Noda; Hiroyuki Kawai (IEEE J. Solid State Circuits, 2013)

A study on micro level traffic prediction for energy-aware routers. - Sou Koyano; Shingo Ata; Hisashi Iwamoto; Yuji Yano; Yasuto Kuroda; Kazunari Inoue; Ikuo Oka (ACM SIGOPS Oper. Syst. Rev., 2013)

Development of onboard LPM-based header processing and reactive link selection for optical packet and circuit integrated networks. - Hideaki Furukawa; Takaya Miyazawa; Hiroaki Harai; Yasuto Kuroda; Shoji Koyama; Shin'ichi Arakawa; Masayuki Murata 001 (ICC, 2014)

Demonstrating 100 Gbps optical packet switching using 16-bit longest prefix matching forwarding engine. - Hideaki Furukawa; Hiroaki Harai; Yasuto Kuroda; Shoji Koyama (ONDM, 2015)

Energy-efficient high-speed search engine using a multi-dimensional TCAM architecture with parallel pipelined subdivided structure. - Masami Nawa; Kenzo Okuda; Shingo Ata; Yasuto Kuroda; Yuji Yano; Hisashi Iwamoto; Kazunari Inoue; Ikuo Oka (CCNC, 2016)

Demonstration of 100 Gbps optical packet switching using header processor based on 48-bit longest prefix matching. - Hideaki Furukawa; Hiroaki Harai; Yasuto Kuroda; Yuji Yano; Shoji Koyama (Photonic Netw. Commun., 2016)