Offset calibrating comparator array for 1.2-V, 6bit, 4-Gsample/s flash ADCs using 0.13μm generic CMOS technology. - Hiroyuki Okada; Yasuyuki Hashimoto; Kohji Sakata; Toshiro Tsukada; Koichiro Ishibashi (ESSCIRC, 2003)

4-Gb/s track and hold circuit using parasitic capacitance canceller [flash ADC application]. - Takahide Sato; Shigetaka Takagi; Nobuo Fujii; Yasuyuki Hashimoto; Kohji Sakata; Hirovuki Okada (ESSCIRC, 2004)

Feedforward-type parasitic capacitance canceler and its application to 4 Gb/s T/H circuit. - Takahide Sato; Shigetaka Takagi; Nobuo Fujii; Yasuyuki Hashimoto; Kohji Sakata; Hiroyuki Okada (ISCAS (6), 2005)

An on-chip active decoupling circuit to suppress crosstalk in deep-submicron CMOS mixed-signal SoCs. - Toshiro Tsukada; Yasuyuki Hashimoto; Kohji Sakata; Hiroyuki Okada; Koichiro Ishibashi (IEEE J. Solid State Circuits, 2005)

Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond. - Koichiro Ishibashi; Tetsuya Fujimoto; Takahiro Yamashita; Hiroyuki Okada; Yukio Arima; Yasuyuki Hashimoto; Kohji Sakata; Isao Minematsu; Yasuo Itoh; Haruki Toda; Motoi Ichihashi; Yoshihide Komatsu; et al. (IEICE Trans. Electron., 2006)