An Open-source Framework for Autonomous SoC Design with Analog Block Generation. - Tutu Ajayi; Sumanth Kamineni; Yaswanth K. Cherivirala; Morteza Fayazi; Kyumin Kwon; Mehdi Saligane; Shourya Gupta; Chien-Hen Chen; Dennis Sylvester; David T. Blaauw; Ronald G. Dreslinski; Benton H. Calhoun; et al. (VLSI-SOC, 2020)

Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation. - Tutu Ajayi; Sumanth Kamineni; Morteza Fayazi; Yaswanth K. Cherivirala; Kyumin Kwon; Shourya Gupta; Wenbo Duan; Jeongsup Lee; Chien-Hen Chen; Mehdi Saligane; Dennis Sylvester; David T. Blaauw; et al. (VLSI-SoC (Selected Papers), 2020)

An Open Source Compatible Framework to Fully Autonomous Digital LDO Generation. - Yaswanth K. Cherivirala; Mehdi Saligane; David D. Wentzloff (ISCAS, 2023)

A Capacitor-Less Digital LDO Regulator With Synthesizable PID Controller Achieving 99.75% Efficiency and 93.3-ps Response Time in 65 nm. - Yaswanth K. Cherivirala; David D. Wentzloff (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A Capacitor-less Hybrid LDO for Low Frequency Supply Noise Suppression Achieving 99.87% Efficiency and 3.32ps Response Time in 65nm. - Yaswanth K. Cherivirala; David D. Wentzloff (ISCAS, 2024)

A Technology-Agnostic Method for Digital LDO Synthesis and Layout Automation. - Yaswanth Kumar Cherivirala; David D. Wentzloff (ISLPED, 2024)

A 1/10 DTC Range Reduction Technique in a Fractional-N MDLL Using a Reference Triggered Ring Oscillator. - Kyumin Kwon; Yaswanth Kumar Cherivirala; David D. Wentzloff (ISCAS, 2025)