Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging. - James W. Tschanz; Nam-Sung Kim; Saurabh Dighe; Jason Howard; Gregory Ruhl; Sriram R. Vangal; Siva G. Narendra; Yatin Hoskote; Howard Wilson; Carol Lam; Matthew Shuman; Carlos Tokunaga; et al. (ISSCC, 2007)

An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS. - Sriram R. Vangal; Jason Howard; Gregory Ruhl; Saurabh Dighe; Howard Wilson; James W. Tschanz; David Finan; Priya Iyer; Arvind P. Singh; Tiju Jacob; Shailendra Jain; Sriram Venkataraman; et al. (ISSCC, 2007)

A 5-GHz Mesh Interconnect for a Teraflops Processor. - Yatin Hoskote; Sriram R. Vangal; Arvind P. Singh; Nitin Borkar; Shekhar Borkar (IEEE Micro, 2007)

Keynote talk II: Designing tomorrow's chips. - Yatin Hoskote (MEMOCODE, 2013)

Edit distance based instruction merging technique to improve flexibility of custom instructions toward flexible accelerator design. - Hui Huang; Taemin Kim; Yatin Hoskote (ASP-DAC, 2014)

Automatic generation of custom SIMD instructions for Superword Level Parallelism. - Taemin Kim; Yatin Hoskote (DATE, 2014)

High level design for wearables and IoT. - Yatin Hoskote; Ilya Klotchkov (ICCAD, 2014)

Design of a low power SoC testchip for wearables and IoTs. - May Wu; Ravi Iyer 001; Yatin Hoskote; Steven Zhang; Julio Zamora-Esquivel; German Fabila Garcia; Ilya Klotchkov; Mukesh Bhartiya (Hot Chips Symposium, 2015)

Learning-Based Power Modeling of System-Level Black-Box IPs. - Dongwook Lee; Taemin Kim; Kyungtae Han; Yatin Hoskote; Lizy K. John; Andreas Gerstlauer (ICCAD, 2015)

A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS. - Tanay Karnik; Dileep Kurian; Paolo A. Aseron; Richard Dorrance; Erkan Alpman; Angela Nicoara; Roman Popov; Leonid Azarenkov; Mikhail J. Moiseev; Li Zhao 002; Santosh Ghosh; Rafael Misoczki; et al. (ISSCC, 2018)