HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform. - Massimo Baleani; Frank Gennari; Yunjian Jiang; Yatish Patel; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (CODES, 2002)

Post-placement C-slow retiming for the xilinx virtex FPGA. - Nicholas Weaver; Yury Markovsky; Yatish Patel; John Wawrzynek (FPGA, 2003)

Exploiting Prediction to Reduce Power on Buses. - Victor Wen; Mark Whitney; Yatish Patel; John Kubiatowicz (HPCA, 2004)

Datapath and control for quantum wires. - Nemanja Isailovic; Mark Whitney; Yatish Patel; John Kubiatowicz; Dean Copsey; Frederic T. Chong; Isaac L. Chuang; Mark Oskin (ACM Trans. Archit. Code Optim., 2004)

Interconnection Networks for Scalable Quantum Computers. - Nemanja Isailovic; Yatish Patel; Mark Whitney; John Kubiatowicz (ISCA, 2006)

Automated generation of layout and control for quantum circuits. - Mark Whitney; Nemanja Isailovic; Yatish Patel; John Kubiatowicz (Conf. Computing Frontiers, 2007)

Running a Quantum Circuit at the Speed of Data. - Nemanja Isailovic; Mark Whitney; Yatish Patel; John Kubiatowicz (ISCA, 2008)

A fault tolerant, area efficient architecture for Shor's factoring algorithm. - Mark Whitney; Nemanja Isailovic; Yatish Patel; John Kubiatowicz (ISCA, 2009)

Using adaptive routing to compensate for performance heterogeneity. - Yury Markovsky; Yatish Patel; John Wawrzynek (NOCS, 2009)

Communication and Control for Quantum Circuits. - Yatish Patel (2010)