A Path Sensitization Approach to Area Reduction. - Hsi-Chuan Chen; Siu-Wing Cheng; Yaun-Chung Hsu; David Hung-Chang Du (ICCD, 1993)

On Valid Clocking for Combinational Circuits. - Shangzhi Sun; David Hung-Chang Du; Yaun-Chung Hsu; Hsi-Chuan Chen (ICCD, 1994)

Timing analysis of combinational circuits containing complex gates. - Yaun-Chung Hsu; Hsi-Chuan Chen; Shangzhi Sun; David Hung-Chang Du (ICCD, 1998)

Finding the longest simple path in cyclic combinational circuits. - Yaun-Chung Hsu; Shangzhi Sun; David Hung-Chang Du (ICCD, 1998)

A technique for minimizing power during FPGA placement. - Kristofer Vorwerk; Madhu Raman; Julien Dunoyer; Yaun-Chung Hsu; Arun Kundu; Andrew A. Kennings (FPL, 2008)