The effect of the digit slicing architecture on the FFT butterfly. - Yazan Samir; Rozita Teymourzadeh (ISSPA, 2010)

FPGA Implementation of pipeline Digit-Slicing Multiplier-Less Radix 2 power of 2 DIF SDF Butterfly for Fourier Transform Structure. - Yazan Samir Algnabi; Rozita Teymourzadeh; Masuri Othman; Md. Shabiul Islam (CoRR, 2018)

Novel Architecture of Pipeline Radix 2 power of 2 SDF FFT Based on Digit-Slicing Technique. - Yazan Samir Algnabi; Furat A. Aldaamee; Rozita Teymourzadeh (CoRR, 2018)

VLSI Implementation of Novel Class of High Speed Pipelined Digital Signal Processing Filter for Wireless Receivers. - Rozita Teymourzadeh; Yazan Samir Algnabi; Masuri Othman; Md. Shabiul Islam; Mok Vee Hong (CoRR, 2018)