Designing a Coarse-Grained Reconfigurable Architecture Using Loop Self-Pipelining. - Jinhui Xu 002; Guiming Wu; Yong Dou; Yazhuo Dong (Asia-Pacific Computer Systems Architecture Conference, 2006)

Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable Hardware. - Yazhuo Dong; Yong Dou; Jie Zhou 007 (ARC, 2007)

A Parameterized Architecture Model in High Level Synthesis for Image Processing Applications. - Yazhuo Dong; Yong Dou (ASP-DAC, 2007)

Hybrid-Mode Floating-Point FPGA CORDIC Co-processor. - Jie Zhou 007; Yong Dou; Yuanwu Lei; Yazhuo Dong (ARC, 2008)

Double Precision Hybrid-Mode Floating-Point FPGA CORDIC Co-processor. - Jie Zhou 007; Yong Dou; Yuanwu Lei; Jinbo Xu; Yazhuo Dong (HPCC, 2008)

Dynamic Configurable Floating-Point FFT Pipelines and Hybrid-Mode CORDIC on FPGA. - Jie Zhou 007; Yazhuo Dong; Yong Dou; Yuanwu Lei (ICESS, 2008)

Pipeline template and scheduling algorithm for mapping multiple loop nests on FPGA with limited resources. - Yazhuo Dong; Wu Zhan; Xiqing Ye (ACM Great Lakes Symposium on VLSI, 2013)

VLIW coprocessor for IEEE-754 quadruple-precision elementary functions. - Yuanwu Lei; Yong Dou; Lei Guo 029; Jinbo Xu; Jie Zhou 007; Yazhuo Dong; Hongjian Li (ACM Trans. Archit. Code Optim., 2013)

FPGA implementation of an exact dot product and its application in variable-precision floating-point arithmetic. - Yuanwu Lei; Yong Dou; Yazhuo Dong; Jie Zhou 007; Fei Xia 003 (J. Supercomput., 2013)