A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-µm CMOS. - Min-Jae Seo; Dong-Hwan Jin; Ye-Dam Kim; Sun-Il Hwang; Jong-Pal Kim; Seung-Tak Ryu (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks. - Min-Jae Seo; Yi-Ju Roh; Dong-Jin Chang; Wan Kim; Ye-Dam Kim; Seung-Tak Ryu (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability. - Min-Jae Seo; Dong-Hwan Jin; Ye-Dam Kim; Jong-Pal Kim; Dong-Jin Chang; Won-Mook Lim; Jae-Hyun Chung; Chang-Un Park; Eun-Ji An; Seung-Tak Ryu (A-SSCC, 2019)

A 6b 28GS/s Four-channel Time-interleaved Current-Steering DAC with Background Clock Phase Calibration. - Woo-Cheol Kim; Dong-Shin Jo; Yi-Ju Roh; Ye-Dam Kim; Seung-Tak Ryu (VLSI Circuits, 2019)

A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC. - Min-Jae Seo; Ye-Dam Kim; Jae-Hyun Chung; Seung-Tak Ryu (VLSI Circuits, 2019)

An 8b 1GS/s 2.55mW SAR-Flash ADC with Complementary Dynamic Amplifiers. - Dong-Ryeol Oh; Kyoung-Jun Moon; Won-Mook Lim; Ye-Dam Kim; Eun-Ji An; Seung-Tak Ryu (VLSI Circuits, 2020)

A Single-Supply CDAC-Based Buffer-Embedding SAR ADC With Skip-Reset Scheme Having Inherent Chopping Capability. - Min-Jae Seo; Dong-Hwan Jin; Ye-Dam Kim; Jong-Pal Kim; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2020)

A 4th-order CT I-DSM with Digital Noise Coupling and Input Pre-conversion Method for Initialization. - Ye-Dam Kim; Jae-Hyun Chung; Kent Edrian Lozada; Dong-Jin Chang; Seung-Tak Ryu (A-SSCC, 2021)

An 8-Bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC With Complementary Dynamic Amplifiers in 28-nm CMOS. - Dong-Ryeol Oh; Kyoung-Jun Moon; Won-Mook Lim; Ye-Dam Kim; Eun-Ji An; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2021)

A 4th-Order Continuous-Time Delta-Sigma Modulator With Hybrid Noise-Coupling. - Kent Edrian Lozada; Il-Hoon Jang; Gyeom-Je Bae; Dong-Hun Lee; Ye-Dam Kim; Hankyu Lee; Seong Joong Kim; Seung-Tak Ryu (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 25kHz-BW 97.4dB-SNDR 100.2dB-DR 3rd-Order SAR-Assisted CT DSM with 1-0 MASH and DNC. - Kent Edrian Lozada; Dong-Hun Lee; Ye-Dam Kim; Ho-Jin Kim; Youngjae Cho; Michael Choi; Seung-Tak Ryu (A-SSCC, 2023)

An 81.2dB-SNDR Dual-Residue Pipeline ADC with a 2nd- Order Noise-Shaping Interpolating SAR ADC. - Jae-Hyun Chung; Ye-Dam Kim; Chang-Un Park; Kun-Woo Park; Min-Jae Seo; Seung-Tak Ryu (CICC, 2023)

A 5× OSR 1MHz-BW 81dB-SNDR 5th-Order Noise-Shaping SAR ADC with Zero-Optimized 3rd-Order Integrator. - Lizhen Zhang; Bo Gao; Kun-Woo Park; Hyeongjin Kim; Kent Edrian Lozada; Ye-Dam Kim; Jianhui Wu 001; Seung-Tak Ryu (A-SSCC, 2024)

A 100kHz-BW 99dB-DR Continuous-Time Tracking-Zoom Incremental ADC with Residue-Gain Switching and Digital NC-FF. - Ye-Dam Kim; Jae-Hyun Chung; Kent Edrian Lozada; Chang-Un Park; Kun-Woo Park; Kwan-Hoon Song; Young-Hun Moon; Min-Jae Seo; Seung-Tak Ryu (VLSI Technology and Circuits, 2024)

A 0.38mW 200kHz-BW 92.1dB-DR Single-Opamp 4th-Order Continuous-Time Delta-Sigma Modulator with 3rd-Order Noise Coupling. - Kent Edrian Lozada; Ye-Dam Kim; Ho-Jin Kim; Youngjae Cho; Michael Choi; Seung-Tak Ryu (VLSI Technology and Circuits, 2024)

A 1.5-MHz BW 81.2-dB SNDR Dual-Residue Pipeline ADC With a Fully Dynamic Noise-Shaping Interpolating-SAR ADC. - Jae-Hyun Chung; Ye-Dam Kim; Chang-Un Park; Kun-Woo Park; Dong-Ryeol Oh; Min-Jae Seo; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2024)

A 25-kHz-BW 97.4-dB-SNDR SAR-Assisted Continuous-Time 1-0 MASH Delta-Sigma Modulator With Digital Noise Coupling. - Dong-Hun Lee; Kent Edrian Lozada; Ye-Dam Kim; Ho-Jin Kim; Youngjae Cho; Michael Choi; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2024)

Continuous-Time Delta-Sigma Modulator with SAR-Assisted Digital Noise Coupling. - Kent Edrian Lozada; Il-Hoon Jang; Ye-Dam Kim; Seung-Tak Ryu (CICC, 2025)

A 0.38-mW 200-kHz-BW Digital-Intensive Single-Opamp Fourth-Order Continuous-Time Delta-Sigma Modulator With Third-Order Digital Noise Coupling in 28-nm CMOS. - Kent Edrian Lozada; Ye-Dam Kim; Ho-Jin Kim; Youngjae Cho; Michael Choi; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2025)