Hierarchical memory scheduling for multimedia MPSoCs. - Ye-Jyun Lin; Chia-Lin Yang; Tay-Jyi Lin; Jiao-Wei Huang; Naehyuck Chang (ICCAD, 2010)

Memory access aware power gating for MPSoCs. - Ye-Jyun Lin; Chia-Lin Yang; Jiao-Wei Huang; Naehyuck Chang (ASP-DAC, 2012)

A buffer cache architecture for smartphones with hybrid DRAM/PCM memory. - Ye-Jyun Lin; Chia-Lin Yang; Hsiang-Pang Li; Cheng-Yuan Michael Wang (NVMSA, 2015)

System-Level Performance and Power Optimization for MPSoC: A Memory Access-Aware Approach. - Ye-Jyun Lin; Chia-Lin Yang; Jiao-Wei Huang; Tay-Jyi Lin; Chih-Wen Hsueh; Naehyuck Chang (ACM Trans. Embed. Comput. Syst., 2015)

A Hybrid DRAM/PCM Buffer Cache Architecture for Smartphones with QoS Consideration. - Ye-Jyun Lin; Chia-Lin Yang; Hsiang-Pang Li; Cheng-Yuan Michael Wang (ACM Trans. Design Autom. Electr. Syst., 2017)