A 15-Bit Quadrature Digital Power Amplifier With Transformer-Based Complex-Domain Efficiency Enhancement. - Yicheng Li 002; Yun Yin; Diyang Zheng; Xianglong Jia; Jie Lin; Fu Gao; Yiting Zhu; Liang Xiong; Na Yan; Ye Lu 005; Hongtao Xu (IEEE J. Solid State Circuits, 2022)

Automated Design of Complex Analog Circuits with Multiagent based Reinforcement Learning. - Jinxin Zhang; Jiarui Bao; Zhangcheng Huang 001; Xuan Zeng 001; Ye Lu 005 (DAC, 2023)

A Combined N/PFET CFET-Based Design and Logic Technology Framework for CMOS Applications. - Xiaona Zhu; Rongzheng Ding; Ouwen Tao; Yage Zhao; Peishun Tang; David Wei Zhang; Ye Lu 005; Shaofeng Yu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Asynchronous Batch Constrained Multi-Objective Bayesian Optimization for Analog Circuit Sizing. - Xuyang Zhao; Zhaori Bi; Changhao Yan; Fan Yang 001; Ye Lu 005; Dian Zhou; Xuan Zeng 001 (ASPDAC, 2024)

EVDMARL: Efficient Value Decomposition-based Multi-Agent Reinforcement Learning with Domain-Randomization for Complex Analog Circuit Design Migration. - Handa Sun; Zhaori Bi; Wenning Jiang; Ye Lu 005; Changhao Yan; Fan Yang 001; Wenchuang Hu; Sheng-Guo Wang; Dian Zhou; Xuan Zeng 001 (DAC, 2024)

A Quadrature Digital Power Amplifier With Wide Efficiency Enhancement Coverage and High Dynamic Power Range. - Yicheng Li 002; Yun Yin; Diyang Zheng; Fu Gao; Jie Lin; Zhen Hu; Ye Lu 005; Hongtao Xu (IEEE J. Solid State Circuits, 2024)

Multiagent Based Reinforcement Learning (MA-RL): An Automated Designer for Complex Analog Circuits. - Jiarui Bao; Jinxin Zhang; Zhangcheng Huang 001; Zhaori Bi; Xingwei Feng; Xuan Zeng 001; Ye Lu 005 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Hierarchical Integration of Reinforcement Learning and Optimization Algorithms for Time-Efficient Design Automation of Complex Analog Circuit. - Xingwei Feng; Yifan Xu; Zhangcheng Huang 001; Wuyi Xu; Zhaori Bi; Fan Yang 001; Xuan Zeng 001; Ye Lu 005 (ACM Trans. Design Autom. Electr. Syst., 2025)

A Cost and Speed Co-Optimized Parallel Stochastic Multiplier for Binary Inputs Supporting Variable Bit-Widths. - Qiang He; Yudi Zhao; Zhihuai Zhang; Gang Du; Xiaofei Nie; Ye Lu 005; Shisheng Xiong; Kai Zhao (IEEE Trans. Circuits Syst. II Express Briefs, 2025)