Layout decomposition with pairwise coloring for multiple patterning lithography. - Ye Zhang 011; Wai-Shing Luk; Hai Zhou 001; Changhao Yan; Xuan Zeng 001 (ICCAD, 2013)

Efficient Statistical Timing Analysis for Circuits with Post-Silicon Tunable Buffers. - Xingbao Zhou; Fan Yang 001; Hai Zhou 001; Min Gong; Hengliang Zhu; Ye Zhang 011; Xuan Zeng 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Layout Decomposition with Pairwise Coloring and Adaptive Multi-Start for Triple Patterning Lithography. - Ye Zhang 011; Wai-Shing Luk; Yunfeng Yang; Hai Zhou 001; Changhao Yan; David Z. Pan; Xuan Zeng 001 (ACM Trans. Design Autom. Electr. Syst., 2015)

Network flow based cut redistribution and insertion for advanced 1D layout design. - Ye Zhang 011; Wai-Shing Luk; Fan Yang 001; Changhao Yan; Hai Zhou 001; Dian Zhou; Xuan Zeng 001 (ASP-DAC, 2017)

A grid-based detailed routing algorithm for advanced 1D process. - Ye Zhang 011; Fan Yang 001; Dian Zhou; Xuan Zeng 001; Xiangdong Hu (ISCAS, 2017)

Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization. - Ye Zhang 011; Wenlong Lyu; Wai-Shing Luk; Fan Yang 001; Hai Zhou 001; Dian Zhou; David Z. Pan; Xuan Zeng 001 (IEEE Trans. Very Large Scale Integr. Syst., 2018)