High voltage tolerant ESD design for analog applications in deep submicron CMOS technologies. - Chung-Hui Chen; Yean-Kuen Fang; Chien-Chun Tsai; Shen Tu; Mark K. L. Chen; Mi-Chang Chang (CICC, 2002)

The impacts of high tensile stress CESL and geometry design on device performance and reliability for 90 nm SOI nMOSFETs. - Chieh-Ming Lai; Yean-Kuen Fang; Chien-Ting Lin; Chia-Wei Hsu; Wen-Kuan Yeh (Microelectron. Reliab., 2007)

Effect of the pre-gate oxide cleaning temperature on the reliability of GOI and devices performances in deep submicron CMOS technology. - Yen-Ting Chiang; Yean-Kuen Fang; Y. J. Huang; Tse-Heng Chou; S. Y. Yeh; C. S. Lin (Microelectron. Reliab., 2008)

Significantly improving sub-90 nm CMOSFET performances with notch-gate enhanced high tensile-stress contact etch stop layer. - Chia-Wei Hsu; Yean-Kuen Fang; Wen-Kuan Yeh; Chien-Ting Lin (Microelectron. Reliab., 2008)

Improvement of TDDB reliability, characteristics of HfO2 high-k/metal gate MOSFET device with oxygen post deposition annealing. - Chia-Wei Hsu; Yean-Kuen Fang; Wen-Kuan Yeh; Chun-Yu Chen; Yen-Ting Chiang; Feng-Renn Juang; Chien-Ting Lin; Chieh-Ming Lai (Microelectron. Reliab., 2010)

Dependence of the Au/SnOx/n-LTPS/glass thin film MOS Schottky diode CO gas sensing performances on operating temperature. - Feng-Renn Juang; Yean-Kuen Fang; Hung-Yu Chiu (Microelectron. Reliab., 2012)

A novel method to improve cell endurance window in source-side injection split gate flash memory. - Yong-Shiuan Tsair; Yean-Kuen Fang; Feng-Renn Juang; Yu-Hsiung Wang; Wen-Ting Chu; Yung-Tao Lin; Luan Tran (Microelectron. Reliab., 2012)

Effect of gate barrier and channel buffer layer on electric properties and transparence of the a-IGZO thin film transistor. - Cheng-I Lin; Yean-Kuen Fang; Wei-Chao Chang; Mao-Wei Chiou; Chih-Wei Chen (Microelectron. Reliab., 2014)