Model Checking Prioritized Timed Automata. - Shang-Wei Lin 001; Pao-Ann Hsiung; Chun-Hsian Huang; Yean-Ru Chen (ATVA, 2005)

Model Checking Timed Systems with Urgencies. - Pao-Ann Hsiung; Shang-Wei Lin 001; Yean-Ru Chen; Chun-Hsian Huang; Jia-Jen Yeh; Hong-Yu Sun; Chao-Sheng Lin; Hsiao-Win Liao (ATVA, 2006)

Modeling and Automatic Failure Analysis of Safety-Critical Systems Using Extended Safecharts. - Yean-Ru Chen; Pao-Ann Hsiung; Sao-Jie Chen (SAFECOMP, 2007)

Automatic Failure Analysis Using Safecharts. - Yean-Ru Chen; Pao-Ann Hsiung (Int. J. Softw. Eng. Knowl. Eng., 2007)

Model Checking Safety-Critical Systems Using Safecharts. - Pao-Ann Hsiung; Yean-Ru Chen; Yen-Hung Lin (IEEE Trans. Computers, 2007)

Compositional Automata Reduction with Non-critical Path Slicing. - Yean-Ru Chen; To-Yu Chen; Pao-Ann Hsiung; Sao-Jie Chen; Yu Hen Hu (FCS, 2009)

VERTAF/Multi-Core: A SysML-Based Application Framework for Multi-Core Embedded Software Development. - Pao-Ann Hsiung; Chao-Sheng Lin; Shang-Wei Lin 001; Yean-Ru Chen; Chun-Hsien Lu; Sheng-Ya Tong; Wan-Ting Su; Chihhsiong Shih; Chorng-Shiuh Koong; Nien-Lin Hsueh; Chih-Hung Chang; William C. Chu (ICA3PP, 2009)

Model-driven development of multi-core embedded software. - Pao-Ann Hsiung; Shang-Wei Lin 001; Yean-Ru Chen; Nien-Lin Hsueh; Chih-Hung Chang; Chihhsiong Shih; Chorng-Shiuh Koong; Chao-Sheng Lin; Chun-Hsien Lu; Sheng-Ya Tong; Wan-Ting Su; William C. Chu (IWMSE@ICSE, 2009)

Modeling and verification of real-time embedded systems with urgency. - Pao-Ann Hsiung; Shang-Wei Lin 001; Yean-Ru Chen; Chun-Hsian Huang; Chihhsiong Shih; William C. Chu (J. Syst. Softw., 2009)

VERTAF/Multi-Core: A SysML-Based Application Framework for Multi-Core Embedded Software Development. - Chao-Sheng Lin; Chun-Hsien Lu; Shang-Wei Lin 001; Yean-Ru Chen; Pao-Ann Hsiung (J. Comput. Sci. Technol., 2011)

Congestion-aware scheduling for NoC-based reconfigurable systems. - Hung-Lin Chao; Yean-Ru Chen; Sheng-Ya Tong; Pao-Ann Hsiung; Sao-Jie Chen (DATE, 2012)

Backward probing deadlock detection for networks-on-chip. - Yean-Ru Chen; Zi-Rong Wangt; Pao-Ann Hsiung; Sao-Jie Chen; Meng-Hsun Tsai (NOCS, 2013)

Unified Security and Safety Risk Assessment - A Case Study on Nuclear Power Plant. - Yean-Ru Chen; Sao-Jie Chen; Pao-Ann Hsiung; I-Hsin Chou (TSA, 2014)

Accelerating Coverage Estimation Through Partial Model Checking. - Yean-Ru Chen; Jia-Jen Yeh; Pao-Ann Hsiung; Sao-Jie Chen (IEEE Trans. Computers, 2014)

Empirical Study of Proposed Meltdown Attack Implementation on BOOM v3. - Chien-Hsiang Lin; Yi-Pei Su; Yean-Ru Chen; Yu-Ting Chou; Sao-Jie Chen (MWSCAS, 2022)

Robustness Analysis of Neural Network Designs for ReLU Family and Batch Normalization. - Hang Chen; Yi-Pei Su; Yean-Ru Chen; Chi-Chieh Chiu; Sao-Jie Chen (TAAI, 2022)

A Study on Traffic Asymmetry for Detecting DDoS Attack in P4-based SDN. - Ting-Yu Lin; Ching-Yuan Wang; Ya-Pei Tuan; Meng-Hsun Tsai; Yean-Ru Chen (J. Inf. Sci. Eng., 2022)

A Quantum SMT Solver for Bit-Vector Theory. - Shang-Wei Lin 001; Si-Han Chen; Tzu-Fan Wang; Yean-Ru Chen (CoRR, 2023)

A Parallel and Distributed Quantum SAT Solver Based on Entanglement and Quantum Teleportation. - Shang-Wei Lin 001; Tzu-Fan Wang; Yean-Ru Chen; Zhe Hou; David Sanán; Yon Shin Teo (CoRR, 2023)

Empirical study on security verification and assessment of neural network accelerator. - Yean-Ru Chen; Tzu-Fan Wang; Si-Han Chen; Yi-Chun Kao (Microprocess. Microsystems, 2023)

SMT Solver With Hardware Acceleration. - Yean-Ru Chen; Si-Han Chen; Shangwei Lin 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

A Parallel and Distributed Quantum SAT Solver Based on Entanglement and Teleportation. - Shang-Wei Lin 001; Tzu-Fan Wang; Yean-Ru Chen; Zhe Hou; David Sanán; Yon Shin Teo (TACAS (2), 2024)

Robustness Analysis of Neural Network Designs with Sparsity Investigation. - Yean-Ru Chen; Chi-Chieh Chiu; Hang Chen (J. Inf. Sci. Eng., 2024)

Markov Clustering-Based Content Placement in Roadside-Unit Caching With Deadline Constraint. - Yu-Ting Wang 002; Ting-Yu Lin; Sok-Ian Sou; Lo-An Chen; Meng-Hsun Tsai; Yean-Ru Chen; Chia-Heng Tu (IEEE Trans. Intell. Transp. Syst., 2024)