Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping. - Jason Cong; Yean-Yow Hwang (FPGA, 1995)

Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design. - Jason Cong; Yean-Yow Hwang (DAC, 1996)

Partially-Dependent Functional Decomposition with Applications in FPGA Synthesis and Mapping. - Jason Cong; Yean-Yow Hwang (FPGA, 1997)

Boolean Matching for Complex PLBs in LUT-based FPGAs with Application to Architecture Evaluation. - Jason Cong; Yean-Yow Hwang (FPGA, 1998)

Intellectual property protection by watermarking combinational logic synthesis solutions. - Darko Kirovski; Yean-Yow Hwang; Miodrag Potkonjak; Jason Cong (ICCAD, 1998)

Technology Mapping for FPGAs with Nonuniform Pin Delays and Fast Interconnections. - Jason Cong; Yean-Yow Hwang; Songjie Xu (DAC, 1999)

Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs. - Jason Cong; Yean-Yow Hwang (ACM Trans. Design Autom. Electr. Syst., 2000)

Boolean matching for LUT-based logic blocks with applications toarchitecture evaluation and technology mapping. - Jason Cong; Yean-Yow Hwang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Protecting Combinational Logic Synthesis Solutions. - Darko Kirovski; Yean-Yow Hwang; Miodrag Potkonjak; Jason Cong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)