A GALS Infrastructure for a Massively Parallel Multiprocessor. - Luis A. Plana; Stephen B. Furber; Steve Temple; Muhammad Mukaram Khan; Yebin Shi; Jian Wu; Shufan Yang (IEEE Des. Test Comput., 2007)

An admission control system for QoS provision on a best-effort GALS interconnect. - Shufan Yang; Steve B. Furber; Yebin Shi; Luis A. Plana (ACSD, 2008)

An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator. - Luis A. Plana; John Bainbridge; Steve B. Furber; Sean Salisbury; Yebin Shi; Jian Wu (NOCS, 2008)

Fault Tolerant Delay Insensitive Inter-chip Communication. - Yebin Shi; Steve B. Furber; Jim D. Garside; Luis A. Plana (ASYNC, 2009)

A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect. - Shufan Yang; Stephen B. Furber; Yebin Shi; Luis A. Plana (Fundam. Informaticae, 2009)

SpiNNaker: Fault tolerance in a power- and area- constrained large-scale neuromimetic architecture. - Javier Navaridas; Steve B. Furber; Jim D. Garside; Xin Jin 003; Mukaram M. Khan; David R. Lester; Mikel Luján; José Miguel-Alonso; Eustace Painkras; Cameron Patterson; Luis A. Plana; Alexander D. Rast; et al. (Parallel Comput., 2013)