Asynchronous Datapath with Software-Controlled On-Chip Adaptive Voltage Scaling for Multirate Signal Processing Application. - Yee William Li; George Patounakis; Anup P. Jose; Kenneth L. Shepard; Steven M. Nowick (ASYNC, 2003)

High-throughput asynchronous datapath with software-controlled voltage scaling. - Yee William Li; George Patounakis; Kenneth L. Shepard; Steven M. Nowick (IEEE J. Solid State Circuits, 2004)

A fully integrated on-chip DC-DC conversion and power management system. - George Patounakis; Yee William Li; Kenneth L. Shepard (IEEE J. Solid State Circuits, 2004)

Continuous-Time Digital Signal Processors. - Yee William Li; Kenneth L. Shepard; Yannis P. Tsividis (ASYNC, 2005)

Continuous-time DSPs, analog/digital computers and other mixed-domain circuits. - Yannis P. Tsividis; Glenn E. R. Cowan; Yee William Li; Kenneth L. Shepard (ESSCIRC, 2005)

A Continuous-Time Programmable Digital FIR Filter. - Yee William Li; Kenneth L. Shepard; Yannis P. Tsividis (IEEE J. Solid State Circuits, 2006)

A 1.05V 1.6mW 0.45°C 3σ-resolution ΔΣ-based temperature sensor with parasitic-resistance compensation in 32nm CMOS. - Y. William Li; Hasnain Lakdawala; Arijit Raychowdhury; Greg Taylor; Krishnamurthy Soumyanath (ISSCC, 2009)

A 1.05 V 1.6 mW, 0.45°C 3σ Resolution ΣΔ Based Temperature Sensor With Parasitic Resistance Compensation in 32 nm Digital CMOS Process. - Hasnain Lakdawala; Y. William Li; Arijit Raychowdhury; Greg Taylor; Krishnamurthy Soumyanath (IEEE J. Solid State Circuits, 2009)

Smart integrated temperature sensor - mixed-signal circuits and systems in 32-nm and beyond. - Y. William Li; Hasnain Lakdawala (CICC, 2011)

A digital fractional-N PLL with a 3mW 0.004mm2 6-bit PVT and mismatch insensitive TDC. - Hyung Seok Kim; Carlos Ornelas; Kailash Chandrashekar; Pin-en Su; Paolo Madoglio; Yee William Li; Ashoke Ravi (ESSCIRC, 2012)

A reconfigurable distributed all-digital clock generator core with SSC and skew correction in 22nm high-k tri-gate LP CMOS. - Y. William Li; Carlos Ornelas; Hyung Seok Kim; Hasnain Lakdawala; Ashoke Ravi; Krishnamurthy Soumyanath (ISSCC, 2012)

A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique. - Hyung Seok Kim; Carlos Ornelas; Kailash Chandrashekar; Dan Shi; Pin-en Su; Paolo Madoglio; Yee William Li; Ashoke Ravi (IEEE J. Solid State Circuits, 2013)

13.6 A 2.4GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applications. - Paolo Madoglio; Hongtao Xu; Kailash Chandrashekar; Luis Cuellar 001; Muhammad Faisal; Yee William Li; Hyung Seok Kim; Khoa Minh Nguyen; Yulin Tan; Brent R. Carlton; Vaibhav A. Vaidya; Yanjie Wang; et al. (ISSCC, 2017)