Model Abstraction for Formal Verification. - Yee-Wing Hsieh; Steven P. Levitan (DATE, 1998)

Control / Data-Flow Analysis for VHDL Semantic Extraction. - Yee-Wing Hsieh; Steven P. Levitan (J. Inf. Sci. Eng., 1998)

Abstraction techniques for verification of multiple tightly coupled counters, registers and comparators. - Yee-Wing Hsieh; Steven P. Levitan (HLDVT, 2000)