Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration. - Wen-Yi Chen; Ming-Dou Ker; Yeh-Jen Huang; Yeh-Ning Jou; Geeng-Lih Lin (APCCAS, 2008)

Improvement on ESD Robustness of Lateral DMOS in High-voltage CMOS ICs by Body Current Injection. - Wen-Yi Chen; Ming-Dou Ker; Yeh-Ning Jou; Yeh-Jen Huang; Geeng-Lih Lin (ISCAS, 2009)

Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection. - Seian-Feng Liao; Kai-Neng Tang; Ming-Dou Ker; Jia-Rong Yeh; Hwa-Chyi Chiou; Yeh-Jen Huang; Chun-Chien Tsai; Yeh-Ning Jou; Geeng-Lih Lin (ECCTD, 2015)

Incorporation of a Simple ESD Circuit in a 650V E-Mode GaN HEMT for All-Terminal ESD Protection. - Jian-Hsing Lee; Yeh-Jen Huang; Li-Yang Hong; Li-Fan Chen; Yeh-Ning Jou; Shin-Cheng Lin; Walter Wohlmuth; Chih-Cherng Liao; Ching-Ho Li; Shoa-Chang Huang; Ke-Horng Chen (IRPS, 2022)

Negative Triggering Current Induced the Latch-up in the Circuit without the ESD device to Power. - Yeh-Jen Huang; Li-Yang Hong; Yeh-Ning Jou; Jian-Hsing Lee (ICCE-Taiwan, 2024)