Analysis of digital bang-bang clock and data recovery for multi-gigabit/s serial transceivers. - Yehui Sun; Hui Wang (CICC, 2009)

2.1 28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS. - Hiroshi Kimura; Pervez M. Aziz; Tai Jing; Ashutosh Sinha; Ram Narayan; Hairong Gao; Ping Jing; Gary Hom; Anshi Liang; Eric Zhang; Aniket Kadkol; Ruchi Kothari; et al. (ISSCC, 2014)

A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS. - Hiroshi Kimura; Pervez M. Aziz; Tai Jing; Ashutosh Sinha; Shiva Prasad Kotagiri; Ram Narayan; Hairong Gao; Ping Jing; Gary Hom; Anshi Liang; Eric Zhang; Aniket Kadkol; et al. (IEEE J. Solid State Circuits, 2014)

Single-Binocular Vision Conversion Strategy for Obstacle Detection at Non-signalized Intersections. - Xiaotian Ma; Xiaoqing Sang; Yehui Sun; Xiaotong Gong; Shanshang Gao; Yi Xu 016; Derong Tan (I-SPAN, 2019)

A 112Gb/s Serial Link Transceiver With 3-tap FFE and 18-tap DFE Receiver for up to 43dB Insertion Loss Channel in 7nm FinFET Technology. - Bo Zhang 029; Anand Vasani; Ashutosh Sinha; Alireza Nilchi; Haitao Tong; Lakshmi P. Rao; Karapet Khanoyan; Hamid Hatamkhani; Xiaochen Yang; Xin Meng; Alexander Wong; Jun Kim; et al. (ISSCC, 2023)

A 112-Gb/s Serial Link Transceiver With Three-Tap FFE and 18-Tap DFE Receiver for up to 43-dB Insertion Loss Channel in 7-nm FinFET Technology. - Bo Zhang 029; Anand Vasani; Ashutosh Sinha; Alireza Nilchi; Haitao Tong; Lakshmi P. Rao; Karapet Khanoyan; Hamid Hatamkhani; Xiaochen Yang; Xin Meng; Alexander Wong; Jun Kim; et al. (IEEE J. Solid State Circuits, 2024)